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A 6b stochastic flash analog-to-digital converter without calibration or reference ladder 一个6b随机闪光模数转换器，没有校准或参考阶梯
2008 IEEE Asian Solid-State Circuits Conference Pub Date : 2008-12-12 DOI: 10.1109/ASSCC.2008.4708805
S. Weaver, B. Hershberg, D. Knierim, U. Moon
{"title":"A 6b stochastic flash analog-to-digital converter without calibration or reference ladder","authors":"S. Weaver, B. Hershberg, D. Knierim, U. Moon","doi":"10.1109/ASSCC.2008.4708805","DOIUrl":"https://doi.org/10.1109/ASSCC.2008.4708805","url":null,"abstract":"A 6-bit stochastic flash ADC is presented. By connecting many comparators in parallel, a reference ladder is avoided by allowing random offset to set individual trip points. The ADC transfer function is the cumulative density function of comparator offset. A technique is proposed to improve transfer function linearity by 8.5 dB. A test chip, fabricated in 0.18 mum CMOS, achieves ENOB over 4.9 b up to 18 MS/s with 900 mV supply and comparator offset standard deviation of 140 mV Comparators are digital cells to allow automated synthesis. Total core power consumption when fs = 8 MHz is 631muW.","PeriodicalId":143173,"journal":{"name":"2008 IEEE Asian Solid-State Circuits Conference","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2008-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125550425","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 37
A 60-GHz, 14% tuning range, multi-band VCO with a single variable inductor 60 ghz, 14%调谐范围，带单变量电感的多频段压控振荡器
2008 IEEE Asian Solid-State Circuits Conference Pub Date : 2008-12-12 DOI: 10.1109/ASSCC.2008.4708746
Chi-Yao Yu, Wei-Zen Chen, Chung-Yu Wu, Tai-You Lu
{"title":"A 60-GHz, 14% tuning range, multi-band VCO with a single variable inductor","authors":"Chi-Yao Yu, Wei-Zen Chen, Chung-Yu Wu, Tai-You Lu","doi":"10.1109/ASSCC.2008.4708746","DOIUrl":"https://doi.org/10.1109/ASSCC.2008.4708746","url":null,"abstract":"This paper presents the design of a 60-GHz, 14% tuning range VCO with a single variable inductor (VID). By employing the proposed frequency tuning scheme, wide-tuning range as well as multi-band operations are achieved without sacrificing its operating frequency. Fabricated in a 90-nm CMOS process, the VCO is capable of covering frequency range from 53.1 to 61.3 GHz. The measured phase noise from a 61.3-GHz carrier is about -118.75 dBc/Hz at 10-MHz offset, and the output power is -6.6 dBm. The VCO core dissipates 8.7 mW from a 0.7-V supply. Chip size is 0.28 times 0.36 mm2.","PeriodicalId":143173,"journal":{"name":"2008 IEEE Asian Solid-State Circuits Conference","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2008-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128769520","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 18
A wide-range all-digital multiphase DLL with supply noise tolerance 一种宽范围全数字多相DLL，具有电源噪声容限
2008 IEEE Asian Solid-State Circuits Conference Pub Date : 2008-12-12 DOI: 10.1109/ASSCC.2008.4708817
Hyunsoo Chae, Dongsuk Shin, Kisoo Kim, Kwan-Weon Kim, Young-Jung Choi, Chulwoo Kim
{"title":"A wide-range all-digital multiphase DLL with supply noise tolerance","authors":"Hyunsoo Chae, Dongsuk Shin, Kisoo Kim, Kwan-Weon Kim, Young-Jung Choi, Chulwoo Kim","doi":"10.1109/ASSCC.2008.4708817","DOIUrl":"https://doi.org/10.1109/ASSCC.2008.4708817","url":null,"abstract":"An 80-to-832 MHz all-digital 8-differential-phase DLL in a 0.18 um CMOS process has been developed to achieve low-jitter and supply noise tolerance using dual window phase detector, noise tolerant delay cell and delay compensation under supply noise. The proposed DLL occupies 0.19 mm2 and dissipates 48 mW at 832 MHz from a 1.8 V supply. The peak-to-peak jitter and rms jitter are 12 ps and 1.73 ps with a quiet supply at 832 MHz, respectively. The peak-to-peak and rms jitter with a 100 mV peak-to-peak triangular supply noise at 100 MHz are 21 ps and 2.99 ps, respectively.","PeriodicalId":143173,"journal":{"name":"2008 IEEE Asian Solid-State Circuits Conference","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2008-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129067665","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
A 1.6mm2 4,096 logic elements multi-context FPGA core in 90nm CMOS 一个1.6mm2 4,096个逻辑元件的90nm CMOS多上下文FPGA核心
2008 IEEE Asian Solid-State Circuits Conference Pub Date : 2008-12-12 DOI: 10.1109/ASSCC.2008.4708736
N. Miyamoto, T. Ohmi
{"title":"A 1.6mm2 4,096 logic elements multi-context FPGA core in 90nm CMOS","authors":"N. Miyamoto, T. Ohmi","doi":"10.1109/ASSCC.2008.4708736","DOIUrl":"https://doi.org/10.1109/ASSCC.2008.4708736","url":null,"abstract":"In this paper, we propose a dynamically reconfigurable multi-context FPGA core named Flexible Processor IV (FP4). FP4 contains 16 times 16 physical logic elements (LE) and 16 context memory planes, thus virtually 4,096 LEs are available in total. The core size is only 1.36 mm times 1.15 mm in 90 nm CMOS technology. A critical issue of FP4 is to prevent the fall of multi-context execution speed. Therefore we have developed a shift-register-type temporal communication module (SR-TCM) and a design automation software named PELOC. PELOC can divide a circuit larger than the physical capacity of FP4 to several smaller sub-circuits while maintaining critical path delay equal among all the sub-circuits. By using the SR-TCM and PELOC, we confirmed that the execution speed of FP4 is almost constant regardless of the number of contexts used.","PeriodicalId":143173,"journal":{"name":"2008 IEEE Asian Solid-State Circuits Conference","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2008-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129133306","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
A 3.2-Gb/s transceiver with a quarter-rate linear phase detector reducing the phase offset 带有四分之一速率线性鉴相器的3.2 gb /s收发器，减少了相位偏移
2008 IEEE Asian Solid-State Circuits Conference Pub Date : 2008-12-12 DOI: 10.1109/ASSCC.2008.4708767
Kyung-Soo Ha, L. Kim
{"title":"A 3.2-Gb/s transceiver with a quarter-rate linear phase detector reducing the phase offset","authors":"Kyung-Soo Ha, L. Kim","doi":"10.1109/ASSCC.2008.4708767","DOIUrl":"https://doi.org/10.1109/ASSCC.2008.4708767","url":null,"abstract":"In this paper, the transceiver which incorporates a PLL using a ring voltage-controlled oscillator (VCO), a phase interpolator (PI), the quarter-rate linear phase detector (PD) and an output driver with pre-emphasis is presented. The phase detector which uses a clock whose frequency is a quarter of the data rate and reduces the phase offset is proposed. The transceiver, implemented in a 0.18-mum CMOS technology, operates at 3.2-Gb/s over a 10-cm PCB line with the bit error rate (BER) of less than 10-12. The chip area is 3.7 times 2.5 mm2 and the core without I/O consumes 45-mA and I/O buffers consume 80-mA from a 1.8-V supply.","PeriodicalId":143173,"journal":{"name":"2008 IEEE Asian Solid-State Circuits Conference","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2008-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128242645","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Aiming for an environmental-oriented CE platform 以环境为导向的CE平台为目标
2008 IEEE Asian Solid-State Circuits Conference Pub Date : 2008-12-12 DOI: 10.1109/ASSCC.2008.4708713
Y. Kushiki
{"title":"Aiming for an environmental-oriented CE platform","authors":"Y. Kushiki","doi":"10.1109/ASSCC.2008.4708713","DOIUrl":"https://doi.org/10.1109/ASSCC.2008.4708713","url":null,"abstract":"I have lived through an epic technological revolution, the digitization of analog products. As a part of that, Panasonic helped to build the digital networking world by developing a semiconductor-based integrated platform, the UniPhier. The twenty-first century will become the ubiquitous + eco-friendly era, in which we will seek drastic energy savings in both products and networks. In the future, we aim to assimilate all of our individual energy-saving technologies into an eco-friendly architecture on the CE platform, and to develop appliances and systems that optimize energy usage in the home. Our concept is an autonomous, coexisting, controllable, decentralized system that incorporates an autonomous optimizing model and embeds an energy management OS. By expanding this system from the home to the social infrastructure, we aim to get closer to realizing a society whose energy usage is optimized for the ecology.","PeriodicalId":143173,"journal":{"name":"2008 IEEE Asian Solid-State Circuits Conference","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2008-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125100621","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Design and performance evaluation of an 8-processor 8,640 MIPS SoC with overhead reduction of interrupt handling in a multi-core system 在多核系统中减少中断处理开销的8处理器8640 MIPS SoC的设计和性能评估
2008 IEEE Asian Solid-State Circuits Conference Pub Date : 2008-12-12 DOI: 10.1109/ASSCC.2008.4708761
Huong Thien Hoang, P. T. Vo, Y. T. Vo, Liem Tan Pham, N. Otsuki, M. Ito, O. Nishii
{"title":"Design and performance evaluation of an 8-processor 8,640 MIPS SoC with overhead reduction of interrupt handling in a multi-core system","authors":"Huong Thien Hoang, P. T. Vo, Y. T. Vo, Liem Tan Pham, N. Otsuki, M. Ito, O. Nishii","doi":"10.1109/ASSCC.2008.4708761","DOIUrl":"https://doi.org/10.1109/ASSCC.2008.4708761","url":null,"abstract":"We have developed a platform SoC including eight SuperH processor cores for high performance applications. It achieves 8,640 MIPS at 600 MHz for Dhrystone 2.1. The eight processor cores are divided into two clusters. Each cluster has a snoop controller to maintain cache coherency. The main internal system bus, packet-based split transaction, is 64 bits wide and runs at 300 MHz. As increasing number of processor cores in the system, enhancing overall system performance and optimizing power are important aims and design challenges. In this paper, we introduce one scheme to improve the system performance by reducing overhead of interrupt handling in multi-core system. We have added an automatic-rotating interrupt distribution scheme to processor cores to reduce overhead in handling interrupt requests. As a result, the processing time in Linux kernel is improved by 21% when SPLASH-2 is executed.","PeriodicalId":143173,"journal":{"name":"2008 IEEE Asian Solid-State Circuits Conference","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2008-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130748103","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A sub-1v low-dropout regulator with an on-chip voltage reference 具有片上基准电压的低于1v的低压差稳压器
2008 IEEE Asian Solid-State Circuits Conference Pub Date : 2008-12-12 DOI: 10.1109/ASSCC.2008.4708754
Wei-Jen Huang, Shen-Iuan Liu
{"title":"A sub-1v low-dropout regulator with an on-chip voltage reference","authors":"Wei-Jen Huang, Shen-Iuan Liu","doi":"10.1109/ASSCC.2008.4708754","DOIUrl":"https://doi.org/10.1109/ASSCC.2008.4708754","url":null,"abstract":"A sub-1V 50 mA low-dropout regulator (LDR) with an on-chip voltage reference is presented. This LDR utilizes the push-pull output stage to reduce the size of the power PMOS transistor. The proposed LDR with the on-chip voltage reference has been fabricated in 0.18 mum CMOS process, and its active area is 0.148 mm2. Experimental results demonstrate that the voltage reference and the LDR work for the supply voltage of 0.6 V~1.2V. For the proposed LDR under a supply of 0.6 V, the measured settling time, voltage dip, and quiescent current are less than 2mus, 50 mV, and 16.6 muA, respectively.","PeriodicalId":143173,"journal":{"name":"2008 IEEE Asian Solid-State Circuits Conference","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2008-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131271518","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A low-noise self-calibrating dynamic comparator for high-speed ADCs 一种用于高速adc的低噪声自校准动态比较器
2008 IEEE Asian Solid-State Circuits Conference Pub Date : 2008-12-12 DOI: 10.1109/ASSCC.2008.4708780
M. Miyahara, Y. Asada, Daehwa Paik, Akira Matsuzawa
{"title":"A low-noise self-calibrating dynamic comparator for high-speed ADCs","authors":"M. Miyahara, Y. Asada, Daehwa Paik, Akira Matsuzawa","doi":"10.1109/ASSCC.2008.4708780","DOIUrl":"https://doi.org/10.1109/ASSCC.2008.4708780","url":null,"abstract":"This paper presents a low offset voltage, low noise dynamic latched comparator using a self-calibrating technique. The new calibration technique does not require any amplifiers for the offset voltage cancellation and quiescent current. It achieves low offset voltage of 1.69 mV at 1 sigma in low power consumption, while 13.7 mV is measured without calibration. Furthermore the proposed comparator requires only one phase clock while conventionally two phase clocks were required leading to relaxed clock. Moreover, a low input noise of 0.6 mV at 1 sigma, three times lower than the conventional one, is obtained. Prototype comparators are realized in 90 nm 10M1P CMOS technology. Experimental and simulated results show that the comparator achieves 1.69 mV offset at 250 MHz operating, while dissipating 40 muW/GHz ( 20 fJ/conv. ) from a 1.0 V supply.","PeriodicalId":143173,"journal":{"name":"2008 IEEE Asian Solid-State Circuits Conference","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2008-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133108400","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 377
An 8mW 10b 50MS/s pipelined ADC using 25dB opamp 一个8mW 10b 50MS/s的流水线ADC，使用25dB运放
2008 IEEE Asian Solid-State Circuits Conference Pub Date : 2008-12-12 DOI: 10.1109/ASSCC.2008.4708726
Min Gyu Kim, V. Kratyuk, P. Hanumolu, G. Ahn, Sunwoo Kwon, U. Moon
{"title":"An 8mW 10b 50MS/s pipelined ADC using 25dB opamp","authors":"Min Gyu Kim, V. Kratyuk, P. Hanumolu, G. Ahn, Sunwoo Kwon, U. Moon","doi":"10.1109/ASSCC.2008.4708726","DOIUrl":"https://doi.org/10.1109/ASSCC.2008.4708726","url":null,"abstract":"In 10-bit 50 MS/s pipelined ADC is presented. A 25 dB open loop dc gain amplifier is employed in the MDAC operation. The low opamp dc gain in the extreme is tolerated due to the use of a reference scaling scheme in conjunction with a background offset calibration. An intermediate gain stage is inserted into the pipeline to compensate for the accumulated reduction of reference and signal swing. The prototype IC implemented in a 90 nm CMOS process achieves -63.2 dB THD, 48.8 dB SNR, and 48.6 dB SNDR, while consuming 8 mW from a 1 V supply.","PeriodicalId":143173,"journal":{"name":"2008 IEEE Asian Solid-State Circuits Conference","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2008-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133373773","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
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