Design and performance evaluation of an 8-processor 8,640 MIPS SoC with overhead reduction of interrupt handling in a multi-core system

Abstract

We have developed a platform SoC including eight SuperH processor cores for high performance applications. It achieves 8,640 MIPS at 600 MHz for Dhrystone 2.1. The eight processor cores are divided into two clusters. Each cluster has a snoop controller to maintain cache coherency. The main internal system bus, packet-based split transaction, is 64 bits wide and runs at 300 MHz. As increasing number of processor cores in the system, enhancing overall system performance and optimizing power are important aims and design challenges. In this paper, we introduce one scheme to improve the system performance by reducing overhead of interrupt handling in multi-core system. We have added an automatic-rotating interrupt distribution scheme to processor cores to reduce overhead in handling interrupt requests. As a result, the processing time in Linux kernel is improved by 21% when SPLASH-2 is executed.