{"title":"7.39mm2 76mW (1944, 972) LDPC解码器芯片,用于IEEE 802.11n应用","authors":"Xin-Yu Shih, Cheng-Zhou Zhan, A. Wu","doi":"10.1109/ASSCC.2008.4708787","DOIUrl":null,"url":null,"abstract":"This paper presents the LDPC decoder chip for (1944,972) QC-LDPC codes in IEEE 802.11n communication system. The efficient LDPC decoder chip is designed with three design techniques, including Group Comparison (GC), Dynamic Wordlength Assignment (DWA), and Data Packet Scheme (DPS). When the target BER is 10-6, the decoding performance can be improved by the coding gain of 0.48 dB and 0.63 dB with respect to (4,3) and (3,2) fixed-point NMSA, respectively. In addition, the total decoder design area can be reduced by 25% and the decoding throughput can be enhanced by 3X times with respect to conventional direct-mapping method. By using TSMC 0.13 um VLSI technology, the core area and die size are only 3.88 mm2 and 7.39 mm2, respectively. The maximum operating frequency is measured at 111.1 MHz and the power dissipation is only 76 mW.","PeriodicalId":143173,"journal":{"name":"2008 IEEE Asian Solid-State Circuits Conference","volume":"76 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2008-12-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"14","resultStr":"{\"title\":\"A 7.39mm2 76mW (1944, 972) LDPC decoder chip for IEEE 802.11n applications\",\"authors\":\"Xin-Yu Shih, Cheng-Zhou Zhan, A. Wu\",\"doi\":\"10.1109/ASSCC.2008.4708787\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents the LDPC decoder chip for (1944,972) QC-LDPC codes in IEEE 802.11n communication system. The efficient LDPC decoder chip is designed with three design techniques, including Group Comparison (GC), Dynamic Wordlength Assignment (DWA), and Data Packet Scheme (DPS). When the target BER is 10-6, the decoding performance can be improved by the coding gain of 0.48 dB and 0.63 dB with respect to (4,3) and (3,2) fixed-point NMSA, respectively. In addition, the total decoder design area can be reduced by 25% and the decoding throughput can be enhanced by 3X times with respect to conventional direct-mapping method. By using TSMC 0.13 um VLSI technology, the core area and die size are only 3.88 mm2 and 7.39 mm2, respectively. The maximum operating frequency is measured at 111.1 MHz and the power dissipation is only 76 mW.\",\"PeriodicalId\":143173,\"journal\":{\"name\":\"2008 IEEE Asian Solid-State Circuits Conference\",\"volume\":\"76 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2008-12-12\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"14\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2008 IEEE Asian Solid-State Circuits Conference\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ASSCC.2008.4708787\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2008 IEEE Asian Solid-State Circuits Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ASSCC.2008.4708787","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 14
摘要
本文介绍了IEEE 802.11n通信系统中(1944,972)QC-LDPC码的LDPC解码器芯片。采用组比较(GC)、动态字长分配(DWA)和数据包方案(DPS)三种设计技术设计了高效LDPC解码器芯片。当目标误码率为10-6时,相对于(4,3)和(3,2)定点NMSA分别增加0.48 dB和0.63 dB的编码增益,可提高译码性能。此外,与传统的直接映射方法相比,解码器的总设计面积可减少25%,解码吞吐量可提高3倍。采用台积电0.13 um VLSI技术,核心面积和芯片尺寸分别仅为3.88 mm2和7.39 mm2。最大工作频率为111.1 MHz,功耗仅为76 mW。
A 7.39mm2 76mW (1944, 972) LDPC decoder chip for IEEE 802.11n applications
This paper presents the LDPC decoder chip for (1944,972) QC-LDPC codes in IEEE 802.11n communication system. The efficient LDPC decoder chip is designed with three design techniques, including Group Comparison (GC), Dynamic Wordlength Assignment (DWA), and Data Packet Scheme (DPS). When the target BER is 10-6, the decoding performance can be improved by the coding gain of 0.48 dB and 0.63 dB with respect to (4,3) and (3,2) fixed-point NMSA, respectively. In addition, the total decoder design area can be reduced by 25% and the decoding throughput can be enhanced by 3X times with respect to conventional direct-mapping method. By using TSMC 0.13 um VLSI technology, the core area and die size are only 3.88 mm2 and 7.39 mm2, respectively. The maximum operating frequency is measured at 111.1 MHz and the power dissipation is only 76 mW.