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2013 IEEE International Conference on Microelectronic Test Structures (ICMTS)最新文献

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Test structure and analysis for accurate RF-characterization of tungsten through silicon via (TSV) grounding devices 钨硅通孔(TSV)接地装置精确rf表征的测试结构与分析
2013 IEEE International Conference on Microelectronic Test Structures (ICMTS) Pub Date : 2013-03-25 DOI: 10.1109/ICMTS.2013.6528141
V. Blaschke, H. Jebory
{"title":"Test structure and analysis for accurate RF-characterization of tungsten through silicon via (TSV) grounding devices","authors":"V. Blaschke, H. Jebory","doi":"10.1109/ICMTS.2013.6528141","DOIUrl":"https://doi.org/10.1109/ICMTS.2013.6528141","url":null,"abstract":"We present an analysis on the extraction of the through silicon via (TSV) inductance from single port and two port S-parameter results. The test structure design is shown to significantly impact the extracted value and could cause inaccurate results and subsequently errors in the Spice model if not accounted for. We will show that an analytical model of the return circuit loop that the TSV forms with the test structure, does provide a useful assessment of the accuracy of the measured results. This analysis further provides important input for test structure design and when to use single port or two port test structures for TSV measurement.","PeriodicalId":142589,"journal":{"name":"2013 IEEE International Conference on Microelectronic Test Structures (ICMTS)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-03-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116918877","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Test structures for electrical evaluation of high aspect ratio TSV arrays fabricated using planarised sacrificial photoresist 平面牺牲光刻胶制造的高纵横比TSV阵列电学评价测试结构
2013 IEEE International Conference on Microelectronic Test Structures (ICMTS) Pub Date : 2013-03-25 DOI: 10.1109/ICMTS.2013.6528142
R. Zhang, Y. Li, J. Murray, A. Bunting, S. Smith, C. Dunare, J. Stevenson, M. Desmulliez, A. Walton
{"title":"Test structures for electrical evaluation of high aspect ratio TSV arrays fabricated using planarised sacrificial photoresist","authors":"R. Zhang, Y. Li, J. Murray, A. Bunting, S. Smith, C. Dunare, J. Stevenson, M. Desmulliez, A. Walton","doi":"10.1109/ICMTS.2013.6528142","DOIUrl":"https://doi.org/10.1109/ICMTS.2013.6528142","url":null,"abstract":"An improved bottom-up electroplating technique has been successfully developed for the fabrication of TSV arrays with 9.5:1 aspect ratios. 125,500 TSVs have been fabricated in an area of 6×6 cm with a horizontal and vertical pitch of 240 μm. A method of visually inspecting the via yield is presented, and Kelvin test structures and contact chain test structures have been fabricated to electrically evaluate single and multiple TSVs respectively. The average resistance of the Cu vias was measured as of 9.1 mΩ using the Kelvin contact resistance structures.","PeriodicalId":142589,"journal":{"name":"2013 IEEE International Conference on Microelectronic Test Structures (ICMTS)","volume":"34 4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-03-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123460612","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Reconsideration of the threshold voltage variability estimated with pair transistor cell array 对双晶体管单元阵列估计阈值电压变异性的重新考虑
2013 IEEE International Conference on Microelectronic Test Structures (ICMTS) Pub Date : 2013-03-25 DOI: 10.1109/ICMTS.2013.6528155
K. Terada, N. Higuchi, K. Tsuji
{"title":"Reconsideration of the threshold voltage variability estimated with pair transistor cell array","authors":"K. Terada, N. Higuchi, K. Tsuji","doi":"10.1109/ICMTS.2013.6528155","DOIUrl":"https://doi.org/10.1109/ICMTS.2013.6528155","url":null,"abstract":"The standard deviation of threshold voltage, σVTH, which is estimated with Pair Transistor cell Array (PTA), is examined using the test chip fabricated by 65-nm technology. It is found that the errors are caused by two problems: 1) the problem in the approximation and 2) leak current in the isolation region. Taking them into account, the application of PTA to the test structure in scribe line is studied.","PeriodicalId":142589,"journal":{"name":"2013 IEEE International Conference on Microelectronic Test Structures (ICMTS)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-03-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117239701","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A proper approach to characterize retention-after-cycling in 3D-Flash devices 描述3D-Flash设备循环后留存率的适当方法
2013 IEEE International Conference on Microelectronic Test Structures (ICMTS) Pub Date : 2013-03-25 DOI: 10.1109/ICMTS.2013.6528169
Fengying Qiao, A. Arreghini, P. Blomme, G. Van den bosch, L. Pan, Jun Xu, J. van Houdt
{"title":"A proper approach to characterize retention-after-cycling in 3D-Flash devices","authors":"Fengying Qiao, A. Arreghini, P. Blomme, G. Van den bosch, L. Pan, Jun Xu, J. van Houdt","doi":"10.1109/ICMTS.2013.6528169","DOIUrl":"https://doi.org/10.1109/ICMTS.2013.6528169","url":null,"abstract":"We propose a procedure to evaluate retention-after-cycling in 3D-Flash devices. Proper comparison of retention transients requires the initial charging level to be as close as possible, but P/E cycling results in serious ID-VG degradation, preventing a consistent extraction of the threshold voltage. We introduce a test where a relaxation phase is added after cycling, consisting in baking samples for 24 hours at 200°C. This relaxation appears to anneal interface traps and to remove locally accumulated charge, restoring similar shape of ID-VG curves before and after cycling, hence allowing a proper comparison of retention of fresh and stressed devices.","PeriodicalId":142589,"journal":{"name":"2013 IEEE International Conference on Microelectronic Test Structures (ICMTS)","volume":"100 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-03-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124858144","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Evaluation of 1/f noise variability in the subthreshold region of MOSFETs mosfet亚阈值区域1/f噪声变异性的评估
2013 IEEE International Conference on Microelectronic Test Structures (ICMTS) Pub Date : 2013-03-25 DOI: 10.1109/ICMTS.2013.6528151
H. Tuinhout, A. Z. Duijnhoven
{"title":"Evaluation of 1/f noise variability in the subthreshold region of MOSFETs","authors":"H. Tuinhout, A. Z. Duijnhoven","doi":"10.1109/ICMTS.2013.6528151","DOIUrl":"https://doi.org/10.1109/ICMTS.2013.6528151","url":null,"abstract":"This paper discusses the challenges of characterization of 1/f noise and its variability under weak-inversion operating conditions of MOSFETs. A dedicated test module was designed with a range of MOSFET types with different layout implementations, particularly focusing at the noise behavior of very wide transistors. Through extensive use of a commercial noise characterization system it proved possible to evaluate the variability of 1/f noise in weak-inversion, revealing several interesting and important subtleties of low frequency noise.","PeriodicalId":142589,"journal":{"name":"2013 IEEE International Conference on Microelectronic Test Structures (ICMTS)","volume":"64 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-03-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134524566","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
A new measurement set-up to investigate the charge trapping phenomena in RF MEMS packaged switches 一种用于研究射频MEMS封装开关中电荷俘获现象的新型测量装置
2013 IEEE International Conference on Microelectronic Test Structures (ICMTS) Pub Date : 2013-03-25 DOI: 10.1109/ICMTS.2013.6528140
M. Barbato, V. Giliberto, G. Meneghesso
{"title":"A new measurement set-up to investigate the charge trapping phenomena in RF MEMS packaged switches","authors":"M. Barbato, V. Giliberto, G. Meneghesso","doi":"10.1109/ICMTS.2013.6528140","DOIUrl":"https://doi.org/10.1109/ICMTS.2013.6528140","url":null,"abstract":"In this work we present a new measurement set up able to predict the lifetime of packaged ohmic RF MEMS submitted to long actuation periods. Experimental results were carried out for a relatively long time period in order to verify the degradation law relates to charge trapping and stiction on cantilever and clamped-clamped switches. Thanks to the use of a microcontroller we have been able to reach a complete control of the timing during the stress phase. Furthermore, the characterization phase has been remarkably reduced in order to minimally influence the charge trapping during the characterization of stressed device. Results are carried out on two different MEMS designs (clamped-clamped and cantilever configurations).","PeriodicalId":142589,"journal":{"name":"2013 IEEE International Conference on Microelectronic Test Structures (ICMTS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-03-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128971773","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
Greek cross test structure for inkjet printed thin films 喷墨印刷薄膜的希腊十字测试结构
2013 IEEE International Conference on Microelectronic Test Structures (ICMTS) Pub Date : 2013-03-25 DOI: 10.1109/ICMTS.2013.6528166
E. Díaz, E. Ramón, J. Carrabina
{"title":"Greek cross test structure for inkjet printed thin films","authors":"E. Díaz, E. Ramón, J. Carrabina","doi":"10.1109/ICMTS.2013.6528166","DOIUrl":"https://doi.org/10.1109/ICMTS.2013.6528166","url":null,"abstract":"This paper reports on usage of Greek cross test structure to characterize geometry of inkjet printed electronics circuits. Geometric characteristics extracted from optical characterization can be correlated with electric measurements for square resistance in order to speed up the characterization processes. Design of inkjet printed Greek cross test structure should consider the ink coalescence and coffee ring effects.","PeriodicalId":142589,"journal":{"name":"2013 IEEE International Conference on Microelectronic Test Structures (ICMTS)","volume":"53 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-03-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129215469","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Mosaic SRAM Cell TEGs with intentionally-added device variability for confirming the ratio-less SRAM operation 马赛克SRAM Cell teg，有意添加设备可变性，以确认无比率SRAM操作
2013 IEEE International Conference on Microelectronic Test Structures (ICMTS) Pub Date : 2013-03-25 DOI: 10.1109/ICMTS.2013.6528174
H. Okamura, T. Saito, H. Goto, M. Yamamoto, K. Nakamura
{"title":"Mosaic SRAM Cell TEGs with intentionally-added device variability for confirming the ratio-less SRAM operation","authors":"H. Okamura, T. Saito, H. Goto, M. Yamamoto, K. Nakamura","doi":"10.1109/ICMTS.2013.6528174","DOIUrl":"https://doi.org/10.1109/ICMTS.2013.6528174","url":null,"abstract":"MOSAIC SRAM Cell TEGs consisting of memory cells having all combinations of gate sizes of transistors differing by two orders of magnitude were developed with 0.18 μm CMOS process to verify the operation margins for SRAM circuits. The measured results show the operation of the ratio-less SRAM is completely independent of the size of transistors in the memory cell.","PeriodicalId":142589,"journal":{"name":"2013 IEEE International Conference on Microelectronic Test Structures (ICMTS)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-03-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127167052","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Newly developed Test-Element-Group for detecting soft failures of the low-resistance-element using doubly nesting array 新开发的Test-Element-Group采用双嵌套阵列检测低阻元件的软故障
2013 IEEE International Conference on Microelectronic Test Structures (ICMTS) Pub Date : 2013-03-25 DOI: 10.1109/ICMTS.2013.6528152
S. Sato, H. Shinkawata, A. Tsuda, T. Yoshizawa, T. Ohno
{"title":"Newly developed Test-Element-Group for detecting soft failures of the low-resistance-element using doubly nesting array","authors":"S. Sato, H. Shinkawata, A. Tsuda, T. Yoshizawa, T. Ohno","doi":"10.1109/ICMTS.2013.6528152","DOIUrl":"https://doi.org/10.1109/ICMTS.2013.6528152","url":null,"abstract":"We report newly developed Test-Element-Group for detecting soft failures of low-resistance-element like interconnect via using doubly nesting array. We detected the soft failure of fine via which resistance had about 10 times larger resistance than normal via using this structure manufactured in 40nm CMOS technology.","PeriodicalId":142589,"journal":{"name":"2013 IEEE International Conference on Microelectronic Test Structures (ICMTS)","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-03-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127224849","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
On the length of THRU standard for TRL de-embedding on Si substrate above 110 GHz 110 GHz以上硅衬底上TRL脱嵌的THRU长度标准
2013 IEEE International Conference on Microelectronic Test Structures (ICMTS) Pub Date : 2013-03-25 DOI: 10.1109/ICMTS.2013.6528150
A. Orii, M. Suizu, S. Amakawa, K. Katayama, K. Takano, M. Motoyoshi, T. Yoshida, M. Fujishima
{"title":"On the length of THRU standard for TRL de-embedding on Si substrate above 110 GHz","authors":"A. Orii, M. Suizu, S. Amakawa, K. Katayama, K. Takano, M. Motoyoshi, T. Yoshida, M. Fujishima","doi":"10.1109/ICMTS.2013.6528150","DOIUrl":"https://doi.org/10.1109/ICMTS.2013.6528150","url":null,"abstract":"It is known that the THRU standard (a transmission line) used for thru-reflect-line (TRL) calibration/de-embedding for S-parameter measurement has to be long enough that only a single electromagnetic mode propagates at its center for it to work reliably. But ideally, TRL standards should occupy as little precious silicon real estate as possible. This paper attempts to experimentally find out how long a THRU is long enough above 110GHz up to 170 GHz through measurements of transmission lines of various lengths. The results indicate that the length of a THRU should be at least 400 micrometers, excluding pads and pad-to-line transitions.","PeriodicalId":142589,"journal":{"name":"2013 IEEE International Conference on Microelectronic Test Structures (ICMTS)","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-03-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133769971","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 15
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