Mosaic SRAM Cell TEGs with intentionally-added device variability for confirming the ratio-less SRAM operation

Abstract

MOSAIC SRAM Cell TEGs consisting of memory cells having all combinations of gate sizes of transistors differing by two orders of magnitude were developed with 0.18 μm CMOS process to verify the operation margins for SRAM circuits. The measured results show the operation of the ratio-less SRAM is completely independent of the size of transistors in the memory cell.