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2013 IEEE International Conference on Microelectronic Test Structures (ICMTS)最新文献

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Analysis of narrow gate to gate space dependence of MOS gate-source/drain capacitance by using contact-less and drawn-out source/drain test structure 利用无接触和长时间源漏测试结构分析MOS栅极源漏电容的窄栅对栅极空间依赖性
2013 IEEE International Conference on Microelectronic Test Structures (ICMTS) Pub Date : 2013-03-25 DOI: 10.1109/ICMTS.2013.6528160
Y. Naruta, S. Kumashiro
{"title":"Analysis of narrow gate to gate space dependence of MOS gate-source/drain capacitance by using contact-less and drawn-out source/drain test structure","authors":"Y. Naruta, S. Kumashiro","doi":"10.1109/ICMTS.2013.6528160","DOIUrl":"https://doi.org/10.1109/ICMTS.2013.6528160","url":null,"abstract":"A new test structure which can provide voltage to the very narrow source/drain region between adjacent gates by drawing out the source/drain silicide layer has been developed. By using the test structure, the dependence of the gate-drain capacitance (Cgd) on the gate-gate space (Lsp) has been successfully measured until the minimum gate pitch where no contact can be placed. Decrease of Cgd with respect to the decrease of Lsp has been observed and its main cause is identified as the decrease of the gate-drain overlap length.","PeriodicalId":142589,"journal":{"name":"2013 IEEE International Conference on Microelectronic Test Structures (ICMTS)","volume":"60 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-03-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130909598","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Comparison of electrical techniques for temperature evaluation in power MOS transistors 功率MOS晶体管温度评估的电学技术比较
2013 IEEE International Conference on Microelectronic Test Structures (ICMTS) Pub Date : 2013-03-25 DOI: 10.1109/ICMTS.2013.6528156
A. Ferrara, P. Steeneken, K. Reimann, A. Heringa, L. Yan, B. Boksteen, M. Swanenberg, G. Koops, A. Scholten, R. Surdeanu, J. Schmitz, R. Hueting
{"title":"Comparison of electrical techniques for temperature evaluation in power MOS transistors","authors":"A. Ferrara, P. Steeneken, K. Reimann, A. Heringa, L. Yan, B. Boksteen, M. Swanenberg, G. Koops, A. Scholten, R. Surdeanu, J. Schmitz, R. Hueting","doi":"10.1109/ICMTS.2013.6528156","DOIUrl":"https://doi.org/10.1109/ICMTS.2013.6528156","url":null,"abstract":"Three electrical techniques (pulsed-gate, AC-conductance and sense-diode) for temperature evaluation in power MOS transistors have been experimentally compared on the same device. The device under test is a silicon-on-insulator (SOI) laterally-diffused MOSFET (LDMOS) design with embedded sense-diodes in the center and at the edge of the device for providing local temperature information. On-wafer measurements have been performed on a thermal chuck in the temperature range 25-200°C to extract self-heating information and predict the junction temperature for different biasing conditions. Good agreement (within 10%) between the different techniques is achieved, evidencing that reliable temperature estimations can be made using each of the proposed electrical techniques. As a result, factors other than experimental accuracy will play a role in the choice of the most adequate technique for the application of interest. Guidelines for this choice are provided in a benchmarking analysis accounting for ease of application, temperature calibration and accuracy of the results.","PeriodicalId":142589,"journal":{"name":"2013 IEEE International Conference on Microelectronic Test Structures (ICMTS)","volume":"2018 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-03-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132352478","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
A novel BJT structure for high- performance analog circuit applications 一种适用于高性能模拟电路的新型BJT结构
2013 IEEE International Conference on Microelectronic Test Structures (ICMTS) Pub Date : 2013-03-25 DOI: 10.1109/ICMTS.2013.6528154
Seon-Man Hwang, H. Kwon, Jae‐Hyung Jang, Ho-Young Kwak, Sungkyu Kwon, Seung-Yong Sung, Jong-Kwan Shin, Jae-Nam Yu, I. Han, Y. Chung, Jung-Hwan Lee, Ga-Won Lee, H. Lee
{"title":"A novel BJT structure for high- performance analog circuit applications","authors":"Seon-Man Hwang, H. Kwon, Jae‐Hyung Jang, Ho-Young Kwak, Sungkyu Kwon, Seung-Yong Sung, Jong-Kwan Shin, Jae-Nam Yu, I. Han, Y. Chung, Jung-Hwan Lee, Ga-Won Lee, H. Lee","doi":"10.1109/ICMTS.2013.6528154","DOIUrl":"https://doi.org/10.1109/ICMTS.2013.6528154","url":null,"abstract":"A novel structure is proposed to improve the matching characteristics of bipolar junction transistor (BJT) based on CMOS technology for high performance analog circuit applications. This paper includes the analysis of electrical and matching characteristics in collector current density (JC), base current density (JB) and current gain (β). Although the collector current density JC of the proposed structure is similar to that of the conventional structure, the base current density JB is lower than that of conventional structure, which results in higher current gain. The matching characteristics of the collector current density and the current gain of the proposed structure showed improvement of about 12.22% and 36.43%, respectively compared with the conventional structure.","PeriodicalId":142589,"journal":{"name":"2013 IEEE International Conference on Microelectronic Test Structures (ICMTS)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-03-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130278605","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Benchmarking of a surface potential based organic thin-film transistor model against C10-DNTT high performance test devices 基于表面电位的有机薄膜晶体管模型与C10-DNTT高性能测试设备的基准测试
2013 IEEE International Conference on Microelectronic Test Structures (ICMTS) Pub Date : 2013-03-25 DOI: 10.1109/ICMTS.2013.6528164
T. Maiti, T. Hayashi, H. Mori, M. Kang, K. Takimiya, M. Miura-Mattausch, H. Mattausch
{"title":"Benchmarking of a surface potential based organic thin-film transistor model against C10-DNTT high performance test devices","authors":"T. Maiti, T. Hayashi, H. Mori, M. Kang, K. Takimiya, M. Miura-Mattausch, H. Mattausch","doi":"10.1109/ICMTS.2013.6528164","DOIUrl":"https://doi.org/10.1109/ICMTS.2013.6528164","url":null,"abstract":"In this paper, a surface potential based compact model for organic thin-film transistors (OTFTs) including both tail and deep trap states across the band gap is presented and benchmarked against measured data from high-performance dinaphtho thieno thiophene (C10-DNTT) based test devices. This model can accurately describe the OTFT test-structure current from week to strong inversion regime.","PeriodicalId":142589,"journal":{"name":"2013 IEEE International Conference on Microelectronic Test Structures (ICMTS)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-03-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121773234","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Characterization of capacitance mismatch using simple difference Charge-based Capacitance measurement (DCBCM) test structure 利用简单差分电荷电容测量(DCBCM)测试结构表征电容失配
2013 IEEE International Conference on Microelectronic Test Structures (ICMTS) Pub Date : 2013-03-25 DOI: 10.1109/ICMTS.2013.6528144
K. Sawada, G. van der Plas, Y. Miyamori, T. Oishi, C. Vladimir, A. Mercha, V. Diederik, H. Ammo
{"title":"Characterization of capacitance mismatch using simple difference Charge-based Capacitance measurement (DCBCM) test structure","authors":"K. Sawada, G. van der Plas, Y. Miyamori, T. Oishi, C. Vladimir, A. Mercha, V. Diederik, H. Ammo","doi":"10.1109/ICMTS.2013.6528144","DOIUrl":"https://doi.org/10.1109/ICMTS.2013.6528144","url":null,"abstract":"We propose a test structure named difference charge-based capacitance measurement (DCBCM) for measuring matching of MOM capacitance with better than 10 atto-farad (aF) accuracy and MOS capacitance with few tens of aF accuracy. The test structure is a derivative of the Charge-based Capacitance measurement (CBCM) technique [1]. In the structure two matched (or intentionally mismatched) capacitors are charged with alternating voltages on one side and on the other side the charges are alternated between two output nodes. We can eliminate parasitic leakage and charge injection components and extract the capacitance difference from the resulting output current that is proportional to the capacitance difference. It is found that mismatch of 20fF MOM capacitances with intentionally 100aF offset can be measured with 7.2aF absolute accuracy. With an adequate input pulse scheme, we also demonstrated a measurement of 100-200fF MOS capacitance mismatch with bias voltage dependence which showed sensitivity of σ = 0.06%. The proposed DCBCM technique is suitable for evaluating small capacitance mismatch for beyond 20nm node.","PeriodicalId":142589,"journal":{"name":"2013 IEEE International Conference on Microelectronic Test Structures (ICMTS)","volume":"104 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-03-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132062847","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Electrical and mechanical characterizations of a large-area, printed organic transistor active matrix with floating-gate-based nonuniformity compensator 带有浮栅非均匀性补偿器的大面积印刷有机晶体管有源矩阵的电学和力学特性
2013 IEEE International Conference on Microelectronic Test Structures (ICMTS) Pub Date : 2013-03-25 DOI: 10.1109/ICMTS.2013.6528165
T. Sekitani, T. Yokota, T. Tokuhara, T. Someya
{"title":"Electrical and mechanical characterizations of a large-area, printed organic transistor active matrix with floating-gate-based nonuniformity compensator","authors":"T. Sekitani, T. Yokota, T. Tokuhara, T. Someya","doi":"10.1109/ICMTS.2013.6528165","DOIUrl":"https://doi.org/10.1109/ICMTS.2013.6528165","url":null,"abstract":"In this paper, we report the testing of the performance variations in a large-scale, printed, ultraflexible organic transistor active matrix on a 10-μm thin-film plastic substrate. A printed active matrix comprising printed floating gate organic transistors has been manufactured using high-definition screen-printing and inkjet-printing. Furthermore, by applying feedback control to the threshold voltages of the floating gate organic transistors, the circuit can be made to compensate for the device-to-device nonuniformity, which is less than 5%. The mechanical characteristics of the printed transistors are also evaluated. As a 10-μm thin film is used as the substrate, critical bending radii of less than 0.5 mm are achieved.","PeriodicalId":142589,"journal":{"name":"2013 IEEE International Conference on Microelectronic Test Structures (ICMTS)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-03-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123789922","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Micromechanical test structures for the characterisation of electroplated NiFe cantilevers and their viability for use in MEMS switching devices 电镀NiFe悬臂梁的微力学测试结构及其在MEMS开关器件中的应用可行性
2013 IEEE International Conference on Microelectronic Test Structures (ICMTS) Pub Date : 2013-03-25 DOI: 10.1109/ICMTS.2013.6528138
Giuseppe Schiavone, S. Smith, J. Murray, J. Terry, M. Desmulliez, A. Walton
{"title":"Micromechanical test structures for the characterisation of electroplated NiFe cantilevers and their viability for use in MEMS switching devices","authors":"Giuseppe Schiavone, S. Smith, J. Murray, J. Terry, M. Desmulliez, A. Walton","doi":"10.1109/ICMTS.2013.6528138","DOIUrl":"https://doi.org/10.1109/ICMTS.2013.6528138","url":null,"abstract":"This paper presents the fabrication of a series of test devices designed to prove the viability of electroplated NiFe freestanding structures for use in magnetically actuated MEMS switches. Preliminary results show promising actuation responses and further release optimisation and testing will enable the quantitative measurement of the desired characteristics. In addition, this will potentially enable the mechanical characterisation of freestanding structures in other materials by means of magnetic actuation, simply by depositing small quantities of NiFe or other magnetic materials in convenient areas of existing devices.","PeriodicalId":142589,"journal":{"name":"2013 IEEE International Conference on Microelectronic Test Structures (ICMTS)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-03-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126749835","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Characterisation and integration of Parylene as an insulating structural layer for high aspect ratio electroplated copper coils 聚对二甲苯作为高纵横比电镀铜线圈绝缘结构层的表征与集成
2013 IEEE International Conference on Microelectronic Test Structures (ICMTS) Pub Date : 2013-03-25 DOI: 10.1109/ICMTS.2013.6528137
R. Walker, E. Sirotkin, I. Schmueser, J. Terry, S. Smith, J. Stevenson, A. Walton
{"title":"Characterisation and integration of Parylene as an insulating structural layer for high aspect ratio electroplated copper coils","authors":"R. Walker, E. Sirotkin, I. Schmueser, J. Terry, S. Smith, J. Stevenson, A. Walton","doi":"10.1109/ICMTS.2013.6528137","DOIUrl":"https://doi.org/10.1109/ICMTS.2013.6528137","url":null,"abstract":"This paper reports the development of processing methods and test structures for the characterisation and evaluation of Parylene-C as an insulating structural layer material for integration with planar micro-inductors. The process involves the filling of high aspect ratio gaps between copper structures with Parylene and subsequent chemical mechanical planarisation. A test chip has been designed to characterise this process and the results presented. Subsequently complete micro-inductors, with magnetic cores, have been fabricated to demonstrate the capability of the process.","PeriodicalId":142589,"journal":{"name":"2013 IEEE International Conference on Microelectronic Test Structures (ICMTS)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-03-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130391194","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Measurements of SRAM sensitivity against AC power noise with effects of device variation 器件变化影响下SRAM对交流电源噪声灵敏度的测量
2013 IEEE International Conference on Microelectronic Test Structures (ICMTS) Pub Date : 2013-03-25 DOI: 10.1109/ICMTS.2013.6528149
T. Sawada, K. Yoshikawa, H. Takata, K. Nii, M. Nagata
{"title":"Measurements of SRAM sensitivity against AC power noise with effects of device variation","authors":"T. Sawada, K. Yoshikawa, H. Takata, K. Nii, M. Nagata","doi":"10.1109/ICMTS.2013.6528149","DOIUrl":"https://doi.org/10.1109/ICMTS.2013.6528149","url":null,"abstract":"SRAM exhibits the sensitivity of false operation against static and sinusoidal supply voltage variation. A measurement system combines direct radio frequency (RF) power injection, on-chip monitoring of voltage variation on power supply lines, and built-in self test of memory read/write operations. The bit error rate (BER) of an SRAM core exponentially increases when the lowest instantaneous voltage on the power supply line of SRAM cells during RF injection linearly decreases. Test dice on wafers at five different process corners in a 1.5 V 90 nm CMOS technology were tested. The minimum allowable voltage with BER of less than a single bit failure in average becomes smaller, thus more tolerant, when n-channel devices are at the slow corner in a conventional 6-transistor SRAM cell. The measurement technique enables to experimentally evaluate dynamic noise margin of SRAM cores in a given technology.","PeriodicalId":142589,"journal":{"name":"2013 IEEE International Conference on Microelectronic Test Structures (ICMTS)","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-03-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134484394","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
A new Ultra-Fast Single Pulse technique (UFSP) for channel effective mobility evaluation in MOSFETs 一种新的用于mosfet通道有效迁移率评估的超快单脉冲技术
2013 IEEE International Conference on Microelectronic Test Structures (ICMTS) Pub Date : 2013-03-25 DOI: 10.1109/ICMTS.2013.6528147
Z. Ji, J. Gillbert, J. F. Zhang, W. Zhang
{"title":"A new Ultra-Fast Single Pulse technique (UFSP) for channel effective mobility evaluation in MOSFETs","authors":"Z. Ji, J. Gillbert, J. F. Zhang, W. Zhang","doi":"10.1109/ICMTS.2013.6528147","DOIUrl":"https://doi.org/10.1109/ICMTS.2013.6528147","url":null,"abstract":"A new technique is proposed for mobility evaluation to overcome the shortcomings of conventional techniques. By measuring Id and Cgc simultaneously within 3 μs, it removes adverse impact of Vd on mobility, avoids cable-switching, and minimizes charge trapping. Furthermore, it can work on highly `leaky' devices without special RF structure. It is shown that mobility can be extracted with gate leakage current density as high as 40 A/cm2. The sources of error are then systematically analyzed. This technique can be easily implemented in Keithley 4200 semiconductor analyzer with two 4225-PMUs and therefore it can serve as a simple and robust tool for accurate mobility exaction for material selection during technology development.","PeriodicalId":142589,"journal":{"name":"2013 IEEE International Conference on Microelectronic Test Structures (ICMTS)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-03-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121611316","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
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