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2013 IEEE International Conference on Microelectronic Test Structures (ICMTS)最新文献

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On-wafer integrated system for fast characterization and parametric test of new-generation Non Volatile Memories 用于新一代非易失性存储器快速表征和参数测试的片上集成系统
2013 IEEE International Conference on Microelectronic Test Structures (ICMTS) Pub Date : 2013-03-25 DOI: 10.1109/ICMTS.2013.6528171
E. Covi, A. Cabrini, L. Vendrame, L. Bortesi, R. Gastaldi, G. Torelli
{"title":"On-wafer integrated system for fast characterization and parametric test of new-generation Non Volatile Memories","authors":"E. Covi, A. Cabrini, L. Vendrame, L. Bortesi, R. Gastaldi, G. Torelli","doi":"10.1109/ICMTS.2013.6528171","DOIUrl":"https://doi.org/10.1109/ICMTS.2013.6528171","url":null,"abstract":"In new and future generations of Non Volatile Memories such as Phase Change Memories (PCMs) and Resistive-RAMs (ReRAMs), having accurate and controllable program pulses is fundamental to adequately characterize the memory cell, since the obtained cell status is a function of the applied pulse parameters. In order to massively test new cells and enhance conventional instrumentation flexibility, an accurate on-chip pulse generator, which is able to provide pulses with different amplitude, falling time, and duration, has been designed, fabricated, and experimentally evaluated. The designed device can generate pulses with amplitude, fall time, and time duration programmable from 0.5 V to 4.5 V, from 10 ns to several μs, and from 50 ns to 350 ns, respectively.","PeriodicalId":142589,"journal":{"name":"2013 IEEE International Conference on Microelectronic Test Structures (ICMTS)","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-03-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129520495","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Optical high frequency test structure and test bench definition for on wafer silicon integrated noise source characterization up to 110 GHz based on Germanium-on-Silicon photodiode 基于硅上锗光电二极管的高达110 GHz的片上硅集成噪声源特性的光学高频测试结构和试验台定义
2013 IEEE International Conference on Microelectronic Test Structures (ICMTS) Pub Date : 2013-03-25 DOI: 10.1109/ICMTS.2013.6528148
S. Oeuvrard, J. Lampin, G. Ducournau, L. Virot, J. Fédéli, J. Hartmann, F. Danneville, Y. Morandini, D. Gloria
{"title":"Optical high frequency test structure and test bench definition for on wafer silicon integrated noise source characterization up to 110 GHz based on Germanium-on-Silicon photodiode","authors":"S. Oeuvrard, J. Lampin, G. Ducournau, L. Virot, J. Fédéli, J. Hartmann, F. Danneville, Y. Morandini, D. Gloria","doi":"10.1109/ICMTS.2013.6528148","DOIUrl":"https://doi.org/10.1109/ICMTS.2013.6528148","url":null,"abstract":"A new Optical-High-Frequency test structure and dedicated test bench have been developed to characterize a Germanium-on-Silicon photodiode intended to be used as an integrated noise source, a first step to high frequency transistor noise figure on-wafer extraction. Continuous wave signals have been measured from these 1550 nm photodiodes, with RF power higher than -20 dBm at 109 GHz.","PeriodicalId":142589,"journal":{"name":"2013 IEEE International Conference on Microelectronic Test Structures (ICMTS)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-03-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126848447","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
A novel silicon interposer for measuring devices requiring complex two-sided contacting 一种新型硅中间体，用于需要复杂双面接触的测量装置
2013 IEEE International Conference on Microelectronic Test Structures (ICMTS) Pub Date : 2013-03-25 DOI: 10.1109/ICMTS.2013.6528143
J. Derakhshandeh, N. Golshani, L. Steenweg, W. van der Vlist, L. Nanver
{"title":"A novel silicon interposer for measuring devices requiring complex two-sided contacting","authors":"J. Derakhshandeh, N. Golshani, L. Steenweg, W. van der Vlist, L. Nanver","doi":"10.1109/ICMTS.2013.6528143","DOIUrl":"https://doi.org/10.1109/ICMTS.2013.6528143","url":null,"abstract":"The design and fabrication process is presented for a novel silicon-based interposer suitable for dies where it is necessary to place multiple contact pads on the both sides of wafer. This interposer transfers all contacts to the same side of the wafer so that the measurement can be done using conventional probe stations for one-sided probing.","PeriodicalId":142589,"journal":{"name":"2013 IEEE International Conference on Microelectronic Test Structures (ICMTS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-03-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125708450","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Tr variance evaluation induced by probing pressure and its stress extraction methodology in 28nm High-K and Metal Gate process 28nm High-K和Metal Gate工艺探测压力诱导的Tr方差评价及其应力提取方法
2013 IEEE International Conference on Microelectronic Test Structures (ICMTS) Pub Date : 2013-03-25 DOI: 10.1109/ICMTS.2013.6528172
T. Okagaki, T. Hasegawa, H. Takashino, M. Fujii, A. Tsuda, K. Shibutani, Y. Deguchi, M. Yokota, K. Onozawa
{"title":"Tr variance evaluation induced by probing pressure and its stress extraction methodology in 28nm High-K and Metal Gate process","authors":"T. Okagaki, T. Hasegawa, H. Takashino, M. Fujii, A. Tsuda, K. Shibutani, Y. Deguchi, M. Yokota, K. Onozawa","doi":"10.1109/ICMTS.2013.6528172","DOIUrl":"https://doi.org/10.1109/ICMTS.2013.6528172","url":null,"abstract":"We discuss characteristics variance in detail, caused by probing stress in 28 nm High-K and Metal Gate process. The Vth variation of nch large size transistor increases by 20% comparing with weak probing pressure (≃ 0). Regarding small size transistors, probing stress impact both on Vth fluctuation and on Tpd fluctuation is small. Moreover, we extracted the space distribution of probing stress quantitatively. It is useful to calibrate a stress simulation methodology and to facilitate evaluation of the mechanical strength of the material.","PeriodicalId":142589,"journal":{"name":"2013 IEEE International Conference on Microelectronic Test Structures (ICMTS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-03-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130662257","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A novel test structure to implement a programmable logic array using split-gate flash memory cells 一种新的测试结构，以实现可编程逻辑阵列的分闸闪存单元
2013 IEEE International Conference on Microelectronic Test Structures (ICMTS) Pub Date : 2013-03-25 DOI: 10.1109/ICMTS.2013.6528170
H. Om'mani, M. Tadayoni, N. Thota, I. Yue, N. Do
{"title":"A novel test structure to implement a programmable logic array using split-gate flash memory cells","authors":"H. Om'mani, M. Tadayoni, N. Thota, I. Yue, N. Do","doi":"10.1109/ICMTS.2013.6528170","DOIUrl":"https://doi.org/10.1109/ICMTS.2013.6528170","url":null,"abstract":"We developed a novel configurable logic array test structure using a highly scalable 3rd generation split-gate flash memory cell that features low power and fast configuration time. This split-gate SuperFlash® configuration element (SCE) has been demonstrated with a 90nm embedded Flash technology. The resulting SCE eliminates the need for esoteric fabrication process, and sensing, and SRAM circuits and reduces configuration time for programmable arrays (PA) such as FPGAs and CPLDs. Additionally, SCE inherently ports the advantages of SST's split-gate Flash memory technology with compact area, low-voltage read operation, low-power poly-to-poly erase and source-side channel hot electron (SSCHE) injection programming mechanisms, along with superior reliability.","PeriodicalId":142589,"journal":{"name":"2013 IEEE International Conference on Microelectronic Test Structures (ICMTS)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-03-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115327733","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Die-to-die and within-die variation extraction for circuit simulation with surface-potential compact model 基于表面电位紧凑模型的电路仿真模间及模内变化提取
2013 IEEE International Conference on Microelectronic Test Structures (ICMTS) Pub Date : 2013-03-25 DOI: 10.1109/ICMTS.2013.6528162
Y. Ohnari, A. A. Khan, A. Dutta, M. Miura-Mattausch, H. Mattausch
{"title":"Die-to-die and within-die variation extraction for circuit simulation with surface-potential compact model","authors":"Y. Ohnari, A. A. Khan, A. Dutta, M. Miura-Mattausch, H. Mattausch","doi":"10.1109/ICMTS.2013.6528162","DOIUrl":"https://doi.org/10.1109/ICMTS.2013.6528162","url":null,"abstract":"A 65nm CMOS TEG for die-to-die and within-die variation analysis is reported. From measured Vth and Ion variation data of transistor pairs, die-to-die and within-die microscopic-parameter variations of a surface-potential model are extracted. Consideration of only five microscopic parameters is found sufficient to capture the channel-length dependence of these variations.","PeriodicalId":142589,"journal":{"name":"2013 IEEE International Conference on Microelectronic Test Structures (ICMTS)","volume":"120 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-03-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128106076","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Three- and four-point Hamer-type MOSFET parameter extraction methods revisited 三点式和四点锤式MOSFET参数提取方法的回顾
2013 IEEE International Conference on Microelectronic Test Structures (ICMTS) Pub Date : 2013-03-25 DOI: 10.1109/ICMTS.2013.6528161
K. Jeppson
{"title":"Three- and four-point Hamer-type MOSFET parameter extraction methods revisited","authors":"K. Jeppson","doi":"10.1109/ICMTS.2013.6528161","DOIUrl":"https://doi.org/10.1109/ICMTS.2013.6528161","url":null,"abstract":"In this paper the three-point Hamer type and four-point Karlsson & Jeppson type MOSFET parameter extraction methods are revisited concerning robustness and selection of data points. The method for fitting models described by rational functions to measured data proposed by Hamming is also discussed and it is shown how this method calculates its weighted data points. An alternative method where MOSFET resistance values are used instead of current values for the extraction procedure is also investigated in an attempt to increase extraction method robustness. Finally, it is shown how the three point extraction method can be applied not only to the triode region but also to the MOSFET saturation region for separating parameters for the body effect and the velocity saturation.","PeriodicalId":142589,"journal":{"name":"2013 IEEE International Conference on Microelectronic Test Structures (ICMTS)","volume":"85 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-03-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121512457","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
A test structure for analysis of temperature distribution in CMOS LSI with sensing device array 一种用于分析具有传感器件阵列的CMOS大规模集成电路温度分布的测试结构
2013 IEEE International Conference on Microelectronic Test Structures (ICMTS) Pub Date : 1900-01-01 DOI: 10.1109/icmts.2013.6528159
T. Matsuda, H. Hanai, H. Iwata, D. Kondo, T. Hatakeyama, M. Ishizuka, T. Ohzone
{"title":"A test structure for analysis of temperature distribution in CMOS LSI with sensing device array","authors":"T. Matsuda, H. Hanai, H. Iwata, D. Kondo, T. Hatakeyama, M. Ishizuka, T. Ohzone","doi":"10.1109/icmts.2013.6528159","DOIUrl":"https://doi.org/10.1109/icmts.2013.6528159","url":null,"abstract":"A test structure for analysis of temperature distribution in CMOS LSI is presented. Fundamental thermal properties of LSI chip were measured and discussed with simulation results. The test structure consists of 24 sensor blocks, each of which has a resistor as an on-chip heater, a p-n diode array for temperature sensing and selector switches. Dependence of heating time and distance from the resistor were analyzed as well as transient phenomena. The test structure can provide an effective methodology for analysis of fundamental thermal properties in LSIs packaged in various ways.","PeriodicalId":142589,"journal":{"name":"2013 IEEE International Conference on Microelectronic Test Structures (ICMTS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123306508","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
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