Die-to-die and within-die variation extraction for circuit simulation with surface-potential compact model

Abstract

A 65nm CMOS TEG for die-to-die and within-die variation analysis is reported. From measured Vth and Ion variation data of transistor pairs, die-to-die and within-die microscopic-parameter variations of a surface-potential model are extracted. Consideration of only five microscopic parameters is found sufficient to capture the channel-length dependence of these variations.