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2013 IEEE International Conference on Microelectronic Test Structures (ICMTS)最新文献

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Comparison of C-V measurement methods for RF-MEMS capacitive switches RF-MEMS电容开关C-V测量方法的比较
2013 IEEE International Conference on Microelectronic Test Structures (ICMTS) Pub Date : 2013-03-25 DOI: 10.1109/ICMTS.2013.6528145
Jiahui Wang, C. Salm, J. Schmitz
{"title":"Comparison of C-V measurement methods for RF-MEMS capacitive switches","authors":"Jiahui Wang, C. Salm, J. Schmitz","doi":"10.1109/ICMTS.2013.6528145","DOIUrl":"https://doi.org/10.1109/ICMTS.2013.6528145","url":null,"abstract":"The applicability of several capacitance-voltage measurement methods is investigated for the on-wafer characterization of RF-MEMS capacitive switches. These devices combine few-picofarad capacitance with a high quality factor. The standard quasistatic and high-frequency measurements are employed, as well as the recently introduced very-low-frequency method. S11 is measured by a network analyzer to calculate the capacitance of the device from radio-frequency measurements. Significant differences are found around the pull-in and pull-out voltages.","PeriodicalId":142589,"journal":{"name":"2013 IEEE International Conference on Microelectronic Test Structures (ICMTS)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-03-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116732608","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Investigation on safe operating area and ESD robustness in a 60-V BCD process with different deep P-Well test structures 不同深p井试验结构下60 v BCD工艺安全作业面积及ESD稳健性研究
2013 IEEE International Conference on Microelectronic Test Structures (ICMTS) Pub Date : 2013-03-25 DOI: 10.1109/ICMTS.2013.6528158
Chia-Tsen Dai, M. Ker
{"title":"Investigation on safe operating area and ESD robustness in a 60-V BCD process with different deep P-Well test structures","authors":"Chia-Tsen Dai, M. Ker","doi":"10.1109/ICMTS.2013.6528158","DOIUrl":"https://doi.org/10.1109/ICMTS.2013.6528158","url":null,"abstract":"Safe operating area (SOA) is one of the noticeable reliability concerns for power MOSFETs during the normal circuit operating conditions. Besides, electrostatic discharge (ESD) reliability is another important reliability issue for the power IC products. To save the silicon area of power IC with high-voltage (HV) devices, it is preferable for HV MOSFET to be self-protected without any additional ESD protection device, and to behave wide SOA region. In this work, the impact of deep P-Well (DPW) structure to the electrical SOA (eSOA) and ESD robustness of HV MOSFET has been investigated in a 0.25-μm 60-V BCD process. DPW structure is used to implement the RESURF (reduced surface field) in MOSFET, which make it be able to sustain the high operating voltage. From the experimental results in silicon chip, the ESD robustness and eSOA of HV MOSFET can be improved by the modified DPW structure.","PeriodicalId":142589,"journal":{"name":"2013 IEEE International Conference on Microelectronic Test Structures (ICMTS)","volume":"53 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-03-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114312389","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
An integrated CMOS-MEMS probe having two-tips per cantilever for individual contact sensing and kelvin measurement with two cantilevers 一个集成的CMOS-MEMS探头，每个悬臂有两个尖端，用于单独的接触传感和开尔文测量，两个悬臂
2013 IEEE International Conference on Microelectronic Test Structures (ICMTS) Pub Date : 2013-03-25 DOI: 10.1109/ICMTS.2013.6528136
K. Hosaka, S. Morishita, I. Mori, M. Kubota, Y. Mita
{"title":"An integrated CMOS-MEMS probe having two-tips per cantilever for individual contact sensing and kelvin measurement with two cantilevers","authors":"K. Hosaka, S. Morishita, I. Mori, M. Kubota, Y. Mita","doi":"10.1109/ICMTS.2013.6528136","DOIUrl":"https://doi.org/10.1109/ICMTS.2013.6528136","url":null,"abstract":"The MEMS-made probe cards can drastically improve semiconductor wafer test quality as compared to traditional tungsten probe. To further take advantage of MEMS technology, the authors propose a CMOS-MEMS integrated probe card, to solve the tradeoff problem of measurement precision and excess pad damage by skating, by 4-terminal (Kelvin) measurement with two-tracks-per-cantilever needle. Putting two tips on each cantilever enables us to detect electrical contact and to decrease skating. And by this structure, electrical properties of a device under test are measured precisely with 4-terminal measurement which can eliminate track resistance and contact resistance. We measured the resistance of a gold thin film. With 2-terminal method, the resistance was measured to be about 74 ohms. However with Kelvin measurement, the resistance was 0.012-0.022 ohms. This result shows the successful implementation of 4-terminal measurement probe with MEMS technology.","PeriodicalId":142589,"journal":{"name":"2013 IEEE International Conference on Microelectronic Test Structures (ICMTS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-03-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129585313","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
Characterization and simulation of NMOS pass transistor reliability for FPGA routing circuits FPGA路由电路中NMOS通管可靠性的表征与仿真
2013 IEEE International Conference on Microelectronic Test Structures (ICMTS) Pub Date : 2013-03-25 DOI: 10.1109/ICMTS.2013.6528175
C. Chen, J. Watt
{"title":"Characterization and simulation of NMOS pass transistor reliability for FPGA routing circuits","authors":"C. Chen, J. Watt","doi":"10.1109/ICMTS.2013.6528175","DOIUrl":"https://doi.org/10.1109/ICMTS.2013.6528175","url":null,"abstract":"In this work, the impact of bias temperature instability is evaluated for routing pass gate circuits. A simple test structure is proposed and measured data is compared to aging models to demonstrate the importance of modeling circuit level aging effects. Aging models which are shown to be accurate at the transistor level are inadequate at the circuit level unless frequency dependent aging effects are taken into account.","PeriodicalId":142589,"journal":{"name":"2013 IEEE International Conference on Microelectronic Test Structures (ICMTS)","volume":"49 8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-03-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123661958","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Effective channel length estimation using charge-based capacitance measurement 有效的信道长度估计使用基于电荷的电容测量
2013 IEEE International Conference on Microelectronic Test Structures (ICMTS) Pub Date : 2013-03-25 DOI: 10.1109/ICMTS.2013.6528146
K. Tsuji, K. Terada
{"title":"Effective channel length estimation using charge-based capacitance measurement","authors":"K. Tsuji, K. Terada","doi":"10.1109/ICMTS.2013.6528146","DOIUrl":"https://doi.org/10.1109/ICMTS.2013.6528146","url":null,"abstract":"An effective channel length is estimated from the capacitance-voltage (C-V) curves of actual size MOSFETs which are measured using charge-based capacitance measurement (CBCM). To evaluate the accurate capacitances between the gate and the channel of sample MOSFETs, their parasitic capacitances are removed by using the test MOSFETs having various channel size and special test structure. A good linear relation between the gate-channel capacitance and the design channel length is obtained and then, the effective channel length is estimated from it. It is found that the obtained effective channel length is shorter than that extracted by the conventional channel resistance method.","PeriodicalId":142589,"journal":{"name":"2013 IEEE International Conference on Microelectronic Test Structures (ICMTS)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-03-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125200976","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Measurement and investigation of thermal properties of the on-chip metallization for integrated power technologies 集成电源技术片上金属化热性能的测量与研究
2013 IEEE International Conference on Microelectronic Test Structures (ICMTS) Pub Date : 2013-03-25 DOI: 10.1109/ICMTS.2013.6528157
M. Pfost, C. Boianceanu, I. Lascau, Dan Simon, S. Sosin
{"title":"Measurement and investigation of thermal properties of the on-chip metallization for integrated power technologies","authors":"M. Pfost, C. Boianceanu, I. Lascau, Dan Simon, S. Sosin","doi":"10.1109/ICMTS.2013.6528157","DOIUrl":"https://doi.org/10.1109/ICMTS.2013.6528157","url":null,"abstract":"DMOS transistors in integrated power technologies are often subject to significant self-heating and thus high temperatures. This can lead to device failure and reduced lifetime. Hence, numerical electro-thermal simulations already during circuit design are used to ensure that the device temperature stays within the accepted range. In such simulations, the influence of the on-chip metallization must be considered correctly. Therefore, accurate temperature measurements for different on-chip metallization configurations are required for simulator calibration. In this paper, we present test structures with different metal layers and via configurations suitable for that purpose. We will discuss how accurate results can be obtained that show even very small differences between structures with a similar thermal behavior. The measurement results, combined with numerical simulations, give also valuable insights into the heat removal capability of the on-chip metallization.","PeriodicalId":142589,"journal":{"name":"2013 IEEE International Conference on Microelectronic Test Structures (ICMTS)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-03-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122118879","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Efficient technique for Si validation of level shifters 电平移位器Si验证的高效技术
2013 IEEE International Conference on Microelectronic Test Structures (ICMTS) Pub Date : 2013-03-25 DOI: 10.1109/ICMTS.2013.6528173
P. Sharma, B. Smith, D. Hall, M. Nelson, U. Lohani
{"title":"Efficient technique for Si validation of level shifters","authors":"P. Sharma, B. Smith, D. Hall, M. Nelson, U. Lohani","doi":"10.1109/ICMTS.2013.6528173","DOIUrl":"https://doi.org/10.1109/ICMTS.2013.6528173","url":null,"abstract":"This paper presents a new structure that uses an addressable parametric array to validate level shifter cells. This structure is very area efficient and allows direct measurement of input and output voltages. Being a parametric structure enabled direct measurement of the output voltages, a critical parameter for level shifters. Experimental data confirmed the utility of this approach, validating level shifters in three different power domains including source biasing on the same 22-pad design. The simulation results show good correlation with the measured data.","PeriodicalId":142589,"journal":{"name":"2013 IEEE International Conference on Microelectronic Test Structures (ICMTS)","volume":"23 6","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-03-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131838890","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
New methodology for drain current local variability characterization using Y function method 用Y函数法表征漏极电流局部变异性的新方法
2013 IEEE International Conference on Microelectronic Test Structures (ICMTS) Pub Date : 2013-03-25 DOI: 10.1109/ICMTS.2013.6528153
L. Rahhal, A. Bajolet, C. Diouf, A. Cros, J. Rosa, N. Planes, G. Ghibaudo
{"title":"New methodology for drain current local variability characterization using Y function method","authors":"L. Rahhal, A. Bajolet, C. Diouf, A. Cros, J. Rosa, N. Planes, G. Ghibaudo","doi":"10.1109/ICMTS.2013.6528153","DOIUrl":"https://doi.org/10.1109/ICMTS.2013.6528153","url":null,"abstract":"Y function is well known to overcome the influence of source/drain series resistance (Rsd) in MOSFETs. In this work we present a new methodology for drain current local variability characterization using Y function method. Thus, we show that the study of Y function statistical variability permits the extraction of threshold voltage (VTH) and current gain factor (β) local variability without the influence of Rsd values. We also demonstrate a simple drain current local variability model taking into account the influence of Rsd and its variability in strong inversion regime. This new VTH and β extraction method, and drain current variability model were applied with success to advanced FDSOI and Bulk devices with different dimensions.","PeriodicalId":142589,"journal":{"name":"2013 IEEE International Conference on Microelectronic Test Structures (ICMTS)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-03-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131832934","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 18
Process control monitors for individual single-walled carbon nanotube transistor fabrication processes 单个单壁碳纳米管晶体管制造工艺的过程控制监视器
2013 IEEE International Conference on Microelectronic Test Structures (ICMTS) Pub Date : 2013-03-25 DOI: 10.1109/ICMTS.2013.6528167
K. Chikkadi, M. Haluska, C. Hierold, C. Roman
{"title":"Process control monitors for individual single-walled carbon nanotube transistor fabrication processes","authors":"K. Chikkadi, M. Haluska, C. Hierold, C. Roman","doi":"10.1109/ICMTS.2013.6528167","DOIUrl":"https://doi.org/10.1109/ICMTS.2013.6528167","url":null,"abstract":"The manufacturing yield of carbon nanotube transistors is very sensitive to changes in fabrication process parameters, while controlling length, density and orientation of nanotubes simultaneously is still proving elusive in batch fabrication processes. Here, we show an electrode design with a yield of up to 45% working transistors despite our batch fabrication process being based on randomly grown nanotubes. Transistor parameter distributions of 765 devices are shown, demonstrating the potential of our design for process monitoring and control.","PeriodicalId":142589,"journal":{"name":"2013 IEEE International Conference on Microelectronic Test Structures (ICMTS)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-03-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131455181","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Investigation of devices of in-vivo energy harvesting through blood-flow-like excitation 血流样激励体内能量收集装置的研究
2013 IEEE International Conference on Microelectronic Test Structures (ICMTS) Pub Date : 2013-03-25 DOI: 10.1109/ICMTS.2013.6528139
R. O'Keeffe, N. Jackson, A. Mathewson, K. McCarthy
{"title":"Investigation of devices of in-vivo energy harvesting through blood-flow-like excitation","authors":"R. O'Keeffe, N. Jackson, A. Mathewson, K. McCarthy","doi":"10.1109/ICMTS.2013.6528139","DOIUrl":"https://doi.org/10.1109/ICMTS.2013.6528139","url":null,"abstract":"Test structures for energy harvesting through piezoelectric materials are designed using FEM. The results of the modelling are compared to those for fabricated devices which were tested using a perfusion machine to simulate blood flow. The results show considerable accuracy between measured characteristics and simulated ones which only differed by approximately 4%. The modelling also established the best design for energy harvesting using aluminium nitride (AlN) in blood flow.","PeriodicalId":142589,"journal":{"name":"2013 IEEE International Conference on Microelectronic Test Structures (ICMTS)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-03-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121205163","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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