Measurement and investigation of thermal properties of the on-chip metallization for integrated power technologies

Abstract

DMOS transistors in integrated power technologies are often subject to significant self-heating and thus high temperatures. This can lead to device failure and reduced lifetime. Hence, numerical electro-thermal simulations already during circuit design are used to ensure that the device temperature stays within the accepted range. In such simulations, the influence of the on-chip metallization must be considered correctly. Therefore, accurate temperature measurements for different on-chip metallization configurations are required for simulator calibration. In this paper, we present test structures with different metal layers and via configurations suitable for that purpose. We will discuss how accurate results can be obtained that show even very small differences between structures with a similar thermal behavior. The measurement results, combined with numerical simulations, give also valuable insights into the heat removal capability of the on-chip metallization.