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ICECS 2001. 8th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.01EX483)最新文献

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Logic optimization of circuits with pre-defined internal don't cares 具有预定义内部的电路的逻辑优化不关心
ICECS 2001. 8th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.01EX483) Pub Date : 2001-09-02 DOI: 10.1109/ICECS.2001.957724
J. Rau, John T. Wang, Steve Chang
{"title":"Logic optimization of circuits with pre-defined internal don't cares","authors":"J. Rau, John T. Wang, Steve Chang","doi":"10.1109/ICECS.2001.957724","DOIUrl":"https://doi.org/10.1109/ICECS.2001.957724","url":null,"abstract":"During the RTL design, some Satisfiability Don't Cares (SDCs) of a node can be easily identified and specified by designers. Although, in theory, a synthesis tool can extract all SDCs during gate level minimization, the tool may take a lot of effort or be impossible to obtain all SDCs. In addition, some SDCs of a node may not be (directly) useful for minimizing the node but may become useful after some logic transformation on the node. In this paper our first contribution is to describe a method to efficiently utilize those pre-specified SDCs. Several formulae are proposed to describe the \"new\" SDCs after some logic transformations. We also provide an efficient framework to apply these transformed SDCs for optimization. Based on the experimental results for benchmark circuits, we show that the presented methodologies are very encouraging.","PeriodicalId":141392,"journal":{"name":"ICECS 2001. 8th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.01EX483)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-09-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126942197","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
On the analysis of three-conductor transmission lines using Park transformation 三导体输电线路的帕克变换分析
ICECS 2001. 8th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.01EX483) Pub Date : 2001-09-02 DOI: 10.1109/ICECS.2001.957448
S. Leva, A. Morando
{"title":"On the analysis of three-conductor transmission lines using Park transformation","authors":"S. Leva, A. Morando","doi":"10.1109/ICECS.2001.957448","DOIUrl":"https://doi.org/10.1109/ICECS.2001.957448","url":null,"abstract":"Park approach belongs to the usual procedures specific of the modal analysis. Under this point of view it can be used in the analysis of three-phase static components, in particular in the study of symmetric transmission lines. In this case the approach substitutes the matrix formulation, specific of the modal analysis, with space-vectors. In this way we obtain single-phase complex functions able to synthesise all the logic modal processes with much more immediacy and physical visibility in respect to those specific of matrix algebra. In this paper the theoretical aspects are discussed and some application examples are also presented.","PeriodicalId":141392,"journal":{"name":"ICECS 2001. 8th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.01EX483)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-09-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127112695","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Fast half-swing inter-plane circuits for clocked NOR-NOR PLAs 快速半摆平面间电路的时钟NOR-NOR PLAs
ICECS 2001. 8th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.01EX483) Pub Date : 2001-09-02 DOI: 10.1109/ICECS.2001.957723
Chua-Chin Wang, Chih-Chiang Chiu, Yu-Tsung Chien
{"title":"Fast half-swing inter-plane circuits for clocked NOR-NOR PLAs","authors":"Chua-Chin Wang, Chih-Chiang Chiu, Yu-Tsung Chien","doi":"10.1109/ICECS.2001.957723","DOIUrl":"https://doi.org/10.1109/ICECS.2001.957723","url":null,"abstract":"We present two fast half-swing CMOS circuits for NOR-NOR PLA implementation. An additional 1/2 VDD voltage source and buffering transmission gates are inserted between the NOR planes to erase the racing problem and shorten the rise delay as well as the fall delay of the output response such that the speed is enhanced. Besides, the proposed circuit also reveals other advantages of no ground switch, no charge sharing and zero offset.","PeriodicalId":141392,"journal":{"name":"ICECS 2001. 8th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.01EX483)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-09-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125458268","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Adaptive interference reduction in nerve cuff electrode recordings 自适应干扰减少神经袖电极记录
ICECS 2001. 8th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.01EX483) Pub Date : 2001-09-02 DOI: 10.1109/ICECS.2001.957564
I. Triantis, R. Rieger, John Taylor, N. Donaldson
{"title":"Adaptive interference reduction in nerve cuff electrode recordings","authors":"I. Triantis, R. Rieger, John Taylor, N. Donaldson","doi":"10.1109/ICECS.2001.957564","DOIUrl":"https://doi.org/10.1109/ICECS.2001.957564","url":null,"abstract":"Neural signals (ENG) recorded from insulating cuffs fitted with electrodes and placed around nerve bundles may replace artificial sensors in providing feedback signals in functional electrical stimulation (FES) applications. Typical applications include correction of foot-drop, hand grasp in tetraplegic subjects and bladder voiding in certain types of incontinence. Unfortunately, the ENG signal recorded using this method is on the order of a few /spl mu/V whereas interfering signals can have amplitudes of many mV. Probably the main source of such interference is the Electromyogram (EMG) which is generated by excited muscles near the cuff. A method is presented to reduce the interference pickup in nerve cuff recordings. The gains of differential amplifiers connected to true-tripole nerve cuff recording arrangement are timed adaptively to null the residual EMG. Simulation results show that extraction of the neural signal is possible using this method without the need for additional high order filtering.","PeriodicalId":141392,"journal":{"name":"ICECS 2001. 8th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.01EX483)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-09-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124315593","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Five new high-performance multiplexer-based 1-bit full adder cells 五个新的高性能基于多路复用器的1位全加法器单元
ICECS 2001. 8th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.01EX483) Pub Date : 2001-09-02 DOI: 10.1109/ICECS.2001.957597
A. Al-Sheraidah, B. Alhalabi, H. Bui
{"title":"Five new high-performance multiplexer-based 1-bit full adder cells","authors":"A. Al-Sheraidah, B. Alhalabi, H. Bui","doi":"10.1109/ICECS.2001.957597","DOIUrl":"https://doi.org/10.1109/ICECS.2001.957597","url":null,"abstract":"Five new multiplexer-based architectures for 1-bit full adder cell design are presented. Implementing with the pass-gate CMOS multiplexer, results in five distinct adders. Those adder cells along with the conventional 28-transistor CMOS adder are tested using H-Spice under 6 different frequencies and 6 different loads. Testing results shows the new cells exhibit on average 21.7% increase in sum signal speed, and 19.9% increase in carry out signal speed over the conventional 28-transistor CMOS adder, with power-delay product savings reaching up to 18.4%.","PeriodicalId":141392,"journal":{"name":"ICECS 2001. 8th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.01EX483)","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-09-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127963510","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Multirate digital squarer architectures 多速率数字方框架构
ICECS 2001. 8th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.01EX483) Pub Date : 2001-09-02 DOI: 10.1109/ICECS.2001.957709
Fengqi Yu, A. Willson
{"title":"Multirate digital squarer architectures","authors":"Fengqi Yu, A. Willson","doi":"10.1109/ICECS.2001.957709","DOIUrl":"https://doi.org/10.1109/ICECS.2001.957709","url":null,"abstract":"By using multirate signal processing, we propose interleaved and pipelined architectures for digital squarers. The hardware implementation of the proposed architectures and their complexity are discussed at the gate level. In comparison to a recently proposed divide-and-conquer squarer architecture, and for the same throughput, our squarer's hardware complexity is approximately 15% less for a 16-bit squarer, and 23% less for a 32-bit squarer.","PeriodicalId":141392,"journal":{"name":"ICECS 2001. 8th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.01EX483)","volume":"518 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-09-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127614963","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 18
A 1.2 V 500 MHz 32-bit carry-lookahead adder 一个1.2 V 500 MHz 32位超前进位加法器
ICECS 2001. 8th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.01EX483) Pub Date : 2001-09-02 DOI: 10.1109/ICECS.2001.957587
Kuo-Hsing Cheng, Wen-Shiuan Lee, Yung-Chong Huang
{"title":"A 1.2 V 500 MHz 32-bit carry-lookahead adder","authors":"Kuo-Hsing Cheng, Wen-Shiuan Lee, Yung-Chong Huang","doi":"10.1109/ICECS.2001.957587","DOIUrl":"https://doi.org/10.1109/ICECS.2001.957587","url":null,"abstract":"In this paper a 1.2 V 32-bit carry lookahead adder is proposed for high speed, low voltage applications. The proposed new 32-bit adder uses Non-full Voltage Swing True-Single-Phase-Clocking Logic (NSTSPC) to implement the proposed carry lookahead adder. Because the internal node of NSTSPC was non-full swing, its operation speed would be higher than the conventional TSPC. Moreover, the supply voltage for the new adder is 1.2 V, thus the power dissipation would also be reduced. The 32-bit CLA adder using 0.35 /spl mu/m 1P4M CMOS technology with 1.2 V power supply could be operated at a 500 MHz clock frequency.","PeriodicalId":141392,"journal":{"name":"ICECS 2001. 8th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.01EX483)","volume":"138 12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-09-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128764516","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Synthesis of data transmission circuits starting from behavioral HW descriptions 从行为硬件描述出发的数据传输电路综合
ICECS 2001. 8th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.01EX483) Pub Date : 2001-09-02 DOI: 10.1109/ICECS.2001.957725
W. Lange, W. Rosenstiel
{"title":"Synthesis of data transmission circuits starting from behavioral HW descriptions","authors":"W. Lange, W. Rosenstiel","doi":"10.1109/ICECS.2001.957725","DOIUrl":"https://doi.org/10.1109/ICECS.2001.957725","url":null,"abstract":"Data transmission rates are rising steadily, accompanied by the requirements to shorten the design cycle for faster and more complex VLSI chips containing data transmission and protocol control logic. One procedure to shorten the design cycle is to describe the behavior of a system in a HW description language like VHDL and perform high level synthesis thereafter. We describe a FSM generator (FSM-G) which avoids the usage of a HLS tool and translates the VHDL specifications of data transmission circuits into a behavioral RT VHDL description. The behavioral routing table (RT) description can be further synthesized by an RT- and logic synthesis tool. The results of applying the FSM-G to ATM switch controller modules are shown at the end of this paper.","PeriodicalId":141392,"journal":{"name":"ICECS 2001. 8th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.01EX483)","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-09-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128951849","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Memory efficient pipelined Viterbi decoder with look-ahead trace back 内存高效管道维特比解码器与前瞻性跟踪
ICECS 2001. 8th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.01EX483) Pub Date : 2001-09-02 DOI: 10.1109/ICECS.2001.957588
Jung-Gi Baek, Sang-Hun Yoon, J. Chong
{"title":"Memory efficient pipelined Viterbi decoder with look-ahead trace back","authors":"Jung-Gi Baek, Sang-Hun Yoon, J. Chong","doi":"10.1109/ICECS.2001.957588","DOIUrl":"https://doi.org/10.1109/ICECS.2001.957588","url":null,"abstract":"This paper presents a pipelined Viterbi decoder architecture with look-ahead Trace Back (TB). The pipelined architecture is one of the best choices for high throughput of the Viterbi decoder but requires high hardware complexity. The novel architecture is proposed to reduce the hardware complexity based on look-ahead TB concept in the Viterbi decoder. In the proposed architecture, the TB process is carried out at each stage instead of doing it after the definite stages. Thus, the novel architecture does not need the TB block in the conventional Viterbi decoder and has considerably less hardware complexity. Experimental results show that more than 60% memory can be reduced when the look-ahead TB architecture is used for Viterbi decoder with code rate R=1/2 and constraint length K=7.","PeriodicalId":141392,"journal":{"name":"ICECS 2001. 8th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.01EX483)","volume":"99 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-09-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114890369","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
A scintillator-coated phototransistor pixel sensor with dark current cancellation 具有暗电流抵消的闪烁体涂层光电晶体管像素传感器
ICECS 2001. 8th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.01EX483) Pub Date : 2001-09-02 DOI: 10.1109/ICECS.2001.957563
M. Abdallah, E. Dubaric, H. Nilsson, C. Fröjdh, C. Petersson
{"title":"A scintillator-coated phototransistor pixel sensor with dark current cancellation","authors":"M. Abdallah, E. Dubaric, H. Nilsson, C. Fröjdh, C. Petersson","doi":"10.1109/ICECS.2001.957563","DOIUrl":"https://doi.org/10.1109/ICECS.2001.957563","url":null,"abstract":"An investigation of a prototype integrating phototransistor-based CMOS Active Pixel Sensor (APS) circuit coated with scintillating material for intra-oral dental X-ray imaging is presented. Cancellation of the leakage current using a dummy phototransistor technique was tested and proved efficient. Measured results showed a minimal dark current whose value is in the photodiodes ranges. The low values of the leakage current that was achieved together with the low X-ray direct absorption results in a high input dynamic range which, in addition to its high optical sensitivity, makes the phototransistor an excellent candidate to replace the presently dominating CCD systems.","PeriodicalId":141392,"journal":{"name":"ICECS 2001. 8th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.01EX483)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-09-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127162494","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 15
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