快速半摆平面间电路的时钟NOR-NOR PLAs

ICECS 2001. 8th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.01EX483) Pub Date : 2001-09-02 DOI:10.1109/ICECS.2001.957723

Chua-Chin Wang, Chih-Chiang Chiu, Yu-Tsung Chien

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引用次数: 1

摘要

我们提出了两种快速半摆CMOS电路用于NOR-NOR PLA实现。在NOR平面之间插入一个额外的1/2 VDD电压源和缓冲传输门，以消除竞速问题，缩短输出响应的上升延迟和下降延迟，从而提高速度。此外，该电路还具有无接地开关、无电荷共享、零偏移等优点。

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Fast half-swing inter-plane circuits for clocked NOR-NOR PLAs

We present two fast half-swing CMOS circuits for NOR-NOR PLA implementation. An additional 1/2 VDD voltage source and buffering transmission gates are inserted between the NOR planes to erase the racing problem and shorten the rise delay as well as the fall delay of the output response such that the speed is enhanced. Besides, the proposed circuit also reveals other advantages of no ground switch, no charge sharing and zero offset.

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ICECS 2001. 8th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.01EX483)

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