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ICECS 2001. 8th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.01EX483)最新文献

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Effects of analogue ACS implementation errors on the modified feedback decoding algorithm 模拟ACS实现误差对改进反馈译码算法的影响
ICECS 2001. 8th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.01EX483) Pub Date : 2004-04-01 DOI: 10.1109/ICECS.2001.957438
A. Demosthenous, John T. Taylor
{"title":"Effects of analogue ACS implementation errors on the modified feedback decoding algorithm","authors":"A. Demosthenous, John T. Taylor","doi":"10.1109/ICECS.2001.957438","DOIUrl":"https://doi.org/10.1109/ICECS.2001.957438","url":null,"abstract":"Convolutional decoders have long been important in applications where very noisy channels are encountered. The most commonly employed convolutional decoding technique is the Viterbi algorithm (VA). This provides an optimum method for realising a convolutional decoder, but requires a large amount of digital path memory. Recently, the modified feedback decoding algorithm (MFDA) has been suggested as a new alternative approach to the VA. The MFDA requires no digital path memory and so can be realised using mainly analogue components. This paper investigates the effects on the coding performance of the MFDA when its add-compare-select (ACS) block is realised using analogue circuit techniques.","PeriodicalId":141392,"journal":{"name":"ICECS 2001. 8th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.01EX483)","volume":"169 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121142447","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Layout design on multi-finger MOSFET for on-chip ESD protection circuits in a 0.18-/spl mu/m salicided CMOS process 片上ESD保护电路的多指MOSFET的0.18-/spl mu/m碱化CMOS工艺布局设计
ICECS 2001. 8th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.01EX483) Pub Date : 2001-09-02 DOI: 10.1109/ICECS.2001.957754
M. Ker, Che-Hao Chuang, Wen-Yu Lo
{"title":"Layout design on multi-finger MOSFET for on-chip ESD protection circuits in a 0.18-/spl mu/m salicided CMOS process","authors":"M. Ker, Che-Hao Chuang, Wen-Yu Lo","doi":"10.1109/ICECS.2001.957754","DOIUrl":"https://doi.org/10.1109/ICECS.2001.957754","url":null,"abstract":"The layout design to improve uniform ESD current distribution in multi-finger MOSFET devices for better ESD robustness is investigated in a 0.18- /spl mu/m salicided CMOS process. The multi-finger MOSFET, without adding the pick-up guard ring inserted into its source region, or with the vertical direction of power line connection, can sustain a higher ESD level. The layout of I/O cell can be drawn more compactly, but is still able to provide deep-submicron CMOS ICs with higher ESD robustness.","PeriodicalId":141392,"journal":{"name":"ICECS 2001. 8th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.01EX483)","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-09-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115289339","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 23
A CMOS low power voltage controlled oscillator with split-path controller 一种带有分路控制器的CMOS低功率压控振荡器
ICECS 2001. 8th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.01EX483) Pub Date : 2001-09-02 DOI: 10.1109/ICECS.2001.957769
Kuo-Hsing Cheng, Lin-Jiunn Tzou, Wei-Bin Yang, S. Sheu
{"title":"A CMOS low power voltage controlled oscillator with split-path controller","authors":"Kuo-Hsing Cheng, Lin-Jiunn Tzou, Wei-Bin Yang, S. Sheu","doi":"10.1109/ICECS.2001.957769","DOIUrl":"https://doi.org/10.1109/ICECS.2001.957769","url":null,"abstract":"In this paper, the low power VCO is proposed and analyzed. A novel low power voltage controlled oscillator (VCO) is proposed to reduce the total power consumption of the Half-Digital Phase Locked Loop (HDPLL). By Hspice simulation results, the power-frequency ratio of low-power VCO can be reduced over 30% in comparison to conventional VCO. Thus, the novel low power VCO can be used in the low power HDPLL.","PeriodicalId":141392,"journal":{"name":"ICECS 2001. 8th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.01EX483)","volume":"154 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-09-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115301852","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
High-density microelectrode arrays for electrophysiological activity imaging of neuronal networks 用于神经网络电生理活动成像的高密度微电极阵列
ICECS 2001. 8th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.01EX483) Pub Date : 2001-09-02 DOI: 10.1109/ICECS.2001.957439
L. Berdondini, T. Overstolz, N. F. Rooij, M. Koudelka-Hep, M. Wany, P. Seitz
{"title":"High-density microelectrode arrays for electrophysiological activity imaging of neuronal networks","authors":"L. Berdondini, T. Overstolz, N. F. Rooij, M. Koudelka-Hep, M. Wany, P. Seitz","doi":"10.1109/ICECS.2001.957439","DOIUrl":"https://doi.org/10.1109/ICECS.2001.957439","url":null,"abstract":"Presents a new approach to high-density microelectrode arrays for spatially and temporally resolved images of in-vitro neuronal network electrophysiological activity. Based on active pixel sensor technology (APS), the first chip design consists of an array of 64 /spl times/ 64 (4096) pixels on an active area of 2.56 /spl times/ 2.56 mm/sup 2/. Each pixel has a dimension of 40 /spl times/ 40 /spl mu/m/sup 2/ integrating a gold microelectrode of 20 /spl times/ 20 /spl mu/m/sup 2/. An in-pixel differential amplifier locally amplifies the extracellular potential, minimising the electrode-measuring circuit distance. The integrated circuit has a programmable gain and filtering for noise-speed trade-off. The network activity image is obtained by addressing the desired pixels at high sampling frequency and sequentially reading the chip output.","PeriodicalId":141392,"journal":{"name":"ICECS 2001. 8th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.01EX483)","volume":"204 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-09-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115311690","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 31
On algorithm for phoneme speech recognition using nonlinear signal decomposition 基于非线性信号分解的音素语音识别算法研究
ICECS 2001. 8th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.01EX483) Pub Date : 2001-09-02 DOI: 10.1109/ICECS.2001.957442
A. Krot, P. Tkachova, H. Minervina
{"title":"On algorithm for phoneme speech recognition using nonlinear signal decomposition","authors":"A. Krot, P. Tkachova, H. Minervina","doi":"10.1109/ICECS.2001.957442","DOIUrl":"https://doi.org/10.1109/ICECS.2001.957442","url":null,"abstract":"Nonlinear speech signal decomposition based on Volterra-Wiener functional series is described. A possible solution of phoneme recognition problem by means of measuring Wiener kernels is proposed.","PeriodicalId":141392,"journal":{"name":"ICECS 2001. 8th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.01EX483)","volume":"82 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-09-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121052770","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Real time image processing with reconfigurable hardware 实时图像处理与可重构的硬件
ICECS 2001. 8th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.01EX483) Pub Date : 2001-09-02 DOI: 10.1109/ICECS.2001.957718
M. A. Vega-Rodríguez, J. M. Sánchez-Pérez, J. Pulido
{"title":"Real time image processing with reconfigurable hardware","authors":"M. A. Vega-Rodríguez, J. M. Sánchez-Pérez, J. Pulido","doi":"10.1109/ICECS.2001.957718","DOIUrl":"https://doi.org/10.1109/ICECS.2001.957718","url":null,"abstract":"Digital image processing is a very important field within machine vision. Because of it is hard to implement real time image processing operations through software techniques, image processing field is one of the most active areas for reconfigurable computing. This paper introduces a new PCI-based system for real time image processing with reconfigurable hardware. The system uses the HOT2-XL PCI board, and we have implemented a Visual C++ application in order to validate our hardware designs. This environment is based on a library of hardware modules implementing some of the most common operations in image processing. The practical results show that our hardware modules get real time processing, a minimum resource use and a high operation frequency.","PeriodicalId":141392,"journal":{"name":"ICECS 2001. 8th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.01EX483)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-09-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124848630","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 15
Decreasing the minimal sample period for recursive filters implemented using distributed arithmetic 减少使用分布式算法实现递归滤波器的最小采样周期
ICECS 2001. 8th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.01EX483) Pub Date : 2001-09-02 DOI: 10.1109/ICECS.2001.957667
O. Gustafsson, L. Wanhammar
{"title":"Decreasing the minimal sample period for recursive filters implemented using distributed arithmetic","authors":"O. Gustafsson, L. Wanhammar","doi":"10.1109/ICECS.2001.957667","DOIUrl":"https://doi.org/10.1109/ICECS.2001.957667","url":null,"abstract":"For distributed arithmetic the latency is proportional to the maximal number of fractional bits for any coefficient. When implementing recursive filters this is a disadvantage as the resulting minimal sample period may be longer compared with an implementation using separate multiplications and additions. In this paper we propose a method to decrease the latency for inputs where the corresponding coefficient has less fractional bits than the maximal of that distributed arithmetic unit. Further, we show how to utilize this technique to decrease the minimal sample period (iteration period) and how to schedule the distributed arithmetic operations to achieve this lower bound.","PeriodicalId":141392,"journal":{"name":"ICECS 2001. 8th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.01EX483)","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-09-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126093528","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Rapid prototyping of biorthogonal discrete wavelet transforms on FPGAs 双正交离散小波变换在fpga上的快速原型设计
ICECS 2001. 8th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.01EX483) Pub Date : 2001-09-02 DOI: 10.1109/ICECS.2001.957476
M. Nibouche, A. Bouridane, O. Nibouche
{"title":"Rapid prototyping of biorthogonal discrete wavelet transforms on FPGAs","authors":"M. Nibouche, A. Bouridane, O. Nibouche","doi":"10.1109/ICECS.2001.957476","DOIUrl":"https://doi.org/10.1109/ICECS.2001.957476","url":null,"abstract":"The purpose of this paper is to present a methodology for rapid prototyping of biorthogonal wavelet transforms on FPGAs. The methodology is based on adequate partitioning of a time interleaved \"wait cycles\" free architecture. The design has been captured using a schematic capture tools and can be parameterised in terms of the number of filter coefficients, data and coefficient word-lengths, digit size and degree of pipelining. The efficiency of the approach has been verified on the Xilinx 4000 FPGA series.","PeriodicalId":141392,"journal":{"name":"ICECS 2001. 8th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.01EX483)","volume":"60 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-09-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123269068","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
An iterative method for instantaneous frequency estimation 一种瞬时频率估计的迭代方法
ICECS 2001. 8th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.01EX483) Pub Date : 2001-09-02 DOI: 10.1109/ICECS.2001.957460
A. Akan, M. Yalçin, L. Chaparro
{"title":"An iterative method for instantaneous frequency estimation","authors":"A. Akan, M. Yalçin, L. Chaparro","doi":"10.1109/ICECS.2001.957460","DOIUrl":"https://doi.org/10.1109/ICECS.2001.957460","url":null,"abstract":"In this paper, we propose an iterative method to estimate the instantaneous frequency of a signal based on the discrete evolutionary transform (DET). The DET provides a representation for nonstationary signals and a time-frequency kernel that permits us to obtain the time-dependent spectrum of the signal. We will show the instantaneous phase and the corresponding instantaneous frequency (IF) can also be computed from the evolutionary kernel. Estimation of IF is of general interest in time-frequency analysis. Implementation of the IF estimation is done by masking and a recursive nonlinear correction procedure. The proposed estimation is valid for monocomponent as well as multicomponent signals. The estimation procedure is illustrated by means of examples.","PeriodicalId":141392,"journal":{"name":"ICECS 2001. 8th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.01EX483)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-09-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123798781","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
Self-calibrating linear OTAs exemplified in a current mode ADC 自校准线性ota在电流模式ADC的例子
ICECS 2001. 8th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.01EX483) Pub Date : 2001-09-02 DOI: 10.1109/ICECS.2001.957537
R. Wunderlich, R. Frieg, A. Dollberg, K. Schumacher
{"title":"Self-calibrating linear OTAs exemplified in a current mode ADC","authors":"R. Wunderlich, R. Frieg, A. Dollberg, K. Schumacher","doi":"10.1109/ICECS.2001.957537","DOIUrl":"https://doi.org/10.1109/ICECS.2001.957537","url":null,"abstract":"This paper summarizes different approaches for linear operational transconductance amplifiers (linear OTAs). A powerful technique for offset cancellation and transconductance calibration of linear OTAs is shown. The almost ideal linear OTAs can be used in different applications. We introduce the usage in current mode ADCs. Statistical simulations show that the ADC accomplishes 10 bits in a 0.35 /spl mu/m CMOS technology at a single supply voltage of 1.8 V.","PeriodicalId":141392,"journal":{"name":"ICECS 2001. 8th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.01EX483)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-09-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116229561","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
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