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ICECS 2001. 8th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.01EX483)最新文献

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Lead compensation to improve the stability of a two stage rail-to-rail CMOS opamp 引线补偿提高两级轨对轨CMOS运算放大器的稳定性
ICECS 2001. 8th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.01EX483) Pub Date : 2001-09-02 DOI: 10.1109/ICECS.2001.957538
Jean-FranGois Delage, M. Sawan
{"title":"Lead compensation to improve the stability of a two stage rail-to-rail CMOS opamp","authors":"Jean-FranGois Delage, M. Sawan","doi":"10.1109/ICECS.2001.957538","DOIUrl":"https://doi.org/10.1109/ICECS.2001.957538","url":null,"abstract":"The design issues of a two-stage rail-to-rail operational amplifier are discussed in this paper. Current regulation during common mode voltage sweep allows us to apply a lead compensation technique, and a simple scheme enables temperature and process variation robustness. This compensation involves 15 degrees improvement in the phase margin when resistive elements are introduced in the compensation path. The proposed opamp has been implemented and measurements show a 10.4 MHz unity gain bandwidth (GBW) with a minimal phase margin of around 54/spl deg/ for a capacitive load of 35 pF. In addition, a slew rate of about 14 V//spl mu/s is attained and the current consumption is maintained below 530 /spl mu/A.","PeriodicalId":141392,"journal":{"name":"ICECS 2001. 8th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.01EX483)","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-09-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116445063","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A selective compression algorithm for SAR images based on irregular and adaptive sampling 基于不规则采样和自适应采样的SAR图像选择性压缩算法
ICECS 2001. 8th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.01EX483) Pub Date : 2001-09-02 DOI: 10.1109/ICECS.2001.957424
D. Avagnina, F. Dovis, L. Presti, P. Mulassano
{"title":"A selective compression algorithm for SAR images based on irregular and adaptive sampling","authors":"D. Avagnina, F. Dovis, L. Presti, P. Mulassano","doi":"10.1109/ICECS.2001.957424","DOIUrl":"https://doi.org/10.1109/ICECS.2001.957424","url":null,"abstract":"Deals with the topic of selective compression of SAR images. A novel algorithm based on the use of irregular and adaptive sampling is presented: good compression ratios can be achieved selecting the regions of interest (ROI) within the image in order to represent them with an adequate set of samples, while the textured or uniform background is roughly sampled. The method presented has been tested on several SAR images obtaining very good performance. An example of an application is given in this paper.","PeriodicalId":141392,"journal":{"name":"ICECS 2001. 8th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.01EX483)","volume":"152 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-09-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122650921","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A parallel 3D DCT architecture for the compression of integral 3D images 一种用于整体三维图像压缩的并行三维DCT结构
ICECS 2001. 8th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.01EX483) Pub Date : 2001-09-02 DOI: 10.1109/ICECS.2001.957722
A. Aggoun, I. Jalloh
{"title":"A parallel 3D DCT architecture for the compression of integral 3D images","authors":"A. Aggoun, I. Jalloh","doi":"10.1109/ICECS.2001.957722","DOIUrl":"https://doi.org/10.1109/ICECS.2001.957722","url":null,"abstract":"A new VLSI architecture for the computation of the three-dimensional discrete cosine transform (3D DCT) for compression of integral 3D images is proposed. The 3D DCT is decomposed into 1D DCTs computed in each of the three dimensions. The architecture is a parallel structure which computes an N/spl times/N/spl times/N-point DCT by computing N N/spl times/N 2D DCTs in parallel and feeding each of the computed 2D DCT coefficients into a final ID DCT block. The architecture uses 5N/sup 2//2 multiplier-accumulators to evaluate N/spl times/N/spl times/N-point DCT's at a rate of N complete 3D DCT coefficients per clock cycles, where N is even. The architecture is regular and modular and as such it is suitable for VLSI implementation. The proposed architecture has a better area-time performance than previously reported 3D DCT architectures. Also, the proposed architecture reduces the initial delay by a factor of N.","PeriodicalId":141392,"journal":{"name":"ICECS 2001. 8th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.01EX483)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-09-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123012013","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
Statistical properties of number sequences generated by 1D chaotic maps considered as a potential source of pseudorandom number sequences 被认为是伪随机数序列潜在来源的一维混沌映射所产生的数序列的统计性质
ICECS 2001. 8th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.01EX483) Pub Date : 2001-09-02 DOI: 10.1109/ICECS.2001.957776
M. Jessa, M. Walentynowicz
{"title":"Statistical properties of number sequences generated by 1D chaotic maps considered as a potential source of pseudorandom number sequences","authors":"M. Jessa, M. Walentynowicz","doi":"10.1109/ICECS.2001.957776","DOIUrl":"https://doi.org/10.1109/ICECS.2001.957776","url":null,"abstract":"The basic statistical properties of sequences generated by sawtooth maps and tent-like maps as a function of parameter determining the Kolmogorov-Sinai entropy are considered. The statistical properties of sequences generated by both maps for the same value of parameter and the same initial point are also compared. It has been also shown that tent-like maps may have a serious drawback from the perspective of their application as a source of pseudorandom sequences: they cannot generate the maximal-length sequences.","PeriodicalId":141392,"journal":{"name":"ICECS 2001. 8th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.01EX483)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-09-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123034981","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
Multi-window recursive adaptive neural filters 多窗口递归自适应神经滤波器
ICECS 2001. 8th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.01EX483) Pub Date : 2001-09-02 DOI: 10.1109/ICECS.2001.957674
A. Burian, J. Saarinen, P. Kuosmanen
{"title":"Multi-window recursive adaptive neural filters","authors":"A. Burian, J. Saarinen, P. Kuosmanen","doi":"10.1109/ICECS.2001.957674","DOIUrl":"https://doi.org/10.1109/ICECS.2001.957674","url":null,"abstract":"Generalized adaptive neural filters are a class of nonlinear adaptive filters that includes stack filters as a subset. We further extend this class by using a multi-window approach. In this way we obtain a parallel recursive filtering operation and make better use of the implicit parallelism of the neural network architecture. The proposed neural network structure uses shared weight architecture for efficient implementation. Experimental results in actual image processing illustrate the efficiency of the approach.","PeriodicalId":141392,"journal":{"name":"ICECS 2001. 8th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.01EX483)","volume":"183 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-09-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114149011","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Deterministic maximum likelihood method for the localization of near-field sources: algorithm and performance analysis 近场源定位的确定性最大似然法:算法与性能分析
ICECS 2001. 8th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.01EX483) Pub Date : 2001-09-02 DOI: 10.1109/ICECS.2001.957683
Erdinç Çekli, H. A. Çırpan
{"title":"Deterministic maximum likelihood method for the localization of near-field sources: algorithm and performance analysis","authors":"Erdinç Çekli, H. A. Çırpan","doi":"10.1109/ICECS.2001.957683","DOIUrl":"https://doi.org/10.1109/ICECS.2001.957683","url":null,"abstract":"A deterministic maximum likelihood localization algorithm is adapted to estimate the direction of arrival and range parameters of the near field sources. Since the direct maximum likelihood estimation of near-field source parameters results in complicated multi-parameter optimization problems, we reformulated the estimation problem in terms of actual-data sample, called the incomplete data and a hypothetical data set, called the complete data and then devised the expectation/maximization iterative method for obtaining maximum likelihood estimates. The performance analysis of the proposed algorithm is then carried out through the evaluation of Cramer-Rao bounds. Finally, some simulation results are presented.","PeriodicalId":141392,"journal":{"name":"ICECS 2001. 8th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.01EX483)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-09-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128294059","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Cascaded feedforward sigma-delta modulator for wide bandwidth applications 用于宽带应用的级联前馈σ - δ调制器
ICECS 2001. 8th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.01EX483) Pub Date : 2001-09-02 DOI: 10.1109/ICECS.2001.957661
Jen-Shiun Chiang, P. Chou, Teng-Hung Chang
{"title":"Cascaded feedforward sigma-delta modulator for wide bandwidth applications","authors":"Jen-Shiun Chiang, P. Chou, Teng-Hung Chang","doi":"10.1109/ICECS.2001.957661","DOIUrl":"https://doi.org/10.1109/ICECS.2001.957661","url":null,"abstract":"In this paper, we propose a cascaded feedforward sigma-delta modulator for wide bandwidth applications. In our proposed approach, we use a 1.5-bit quantizer as feedback in the multi-bit sigma-delta modulator. The 1.5-bit feedback may cause coarse quantization errors, however the error can be canceled in the digital part. Here an adaptive filter with least mean square algorithm is used to reduce the nonlinear effect. The simulation results show that the SNDR of this architecture is very close to that of the ideal feedforward summation sigma-delta modulator with multi-bit DAC and can be used for the wide bandwidth application.","PeriodicalId":141392,"journal":{"name":"ICECS 2001. 8th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.01EX483)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-09-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128712816","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Si technology in the Internet Era 互联网时代的Si技术
ICECS 2001. 8th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.01EX483) Pub Date : 2001-09-02 DOI: 10.1109/ICECS.2001.957643
D. Buss
{"title":"Si technology in the Internet Era","authors":"D. Buss","doi":"10.1109/ICECS.2001.957643","DOIUrl":"https://doi.org/10.1109/ICECS.2001.957643","url":null,"abstract":"In the PC era, microcomputers (/spl mu/C) and memory were the components that drove growth of the PC industry. In the Internet era, digital signal processors (DSP) and analog processors will be the components that drive growth in Internet products. Over the next 10 years, technology will continue to follow Moore's law of scaling, and in addition, system-on-a-chip (SOC) integration will drive technology. This paper reviews the challenges of continued Moore's law scaling, presents a vision of SOC integration, and makes predictions for the future.","PeriodicalId":141392,"journal":{"name":"ICECS 2001. 8th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.01EX483)","volume":"88 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-09-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129425805","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Asynchronous low power VLSI implementation of the International Data Encryption Algorithm 国际数据加密算法的异步低功耗VLSI实现
ICECS 2001. 8th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.01EX483) Pub Date : 2001-09-02 DOI: 10.1109/ICECS.2001.957482
N. Sklavos, O. Koufopavlou
{"title":"Asynchronous low power VLSI implementation of the International Data Encryption Algorithm","authors":"N. Sklavos, O. Koufopavlou","doi":"10.1109/ICECS.2001.957482","DOIUrl":"https://doi.org/10.1109/ICECS.2001.957482","url":null,"abstract":"An asynchronous VLSI implementation of the International Data Encryption Algorithm (IDEA) is presented in this paper. In order to evaluate the asynchronous design, a synchronous version of the algorithm was also designed. The VHDL hardware description language was used in order to describe the algorithm. By using Synopsys commercially available tools, the VHDL code was synthesized. After placing and routing, both designs were fabricated with 0.6 /spl mu/m CMOS technology. With a system clock of up to 8 MHz and a power supply of 5 V, the two chips were tested and evaluated, comparing them with the software implementation of the IDEA algorithm. This new approach proves efficiently the lower power consumption of the asynchronous implementation compared to the existing synchronous one. Therefore the asynchronous chip performs efficiently in WEP (Wireless Encryption Protocols) and high speed networks.","PeriodicalId":141392,"journal":{"name":"ICECS 2001. 8th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.01EX483)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-09-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129191469","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 24
A divider-multiplier high level synthesis library element for DSP applications 用于DSP应用的除法器-乘法器高级合成库元件
ICECS 2001. 8th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.01EX483) Pub Date : 2001-09-02 DOI: 10.1109/ICECS.2001.957801
M. V. R. Biarge, M. A. Sacristán, A. Álvarez, A. Diaz, V. Peinado, P. Gómez
{"title":"A divider-multiplier high level synthesis library element for DSP applications","authors":"M. V. R. Biarge, M. A. Sacristán, A. Álvarez, A. Diaz, V. Peinado, P. Gómez","doi":"10.1109/ICECS.2001.957801","DOIUrl":"https://doi.org/10.1109/ICECS.2001.957801","url":null,"abstract":"In this paper a divider-multiplier reusable library cell is presented. The division is implemented by means of an algorithm based on successive multiplications. The resulting structure uses a fixed-point format and two's complement arithmetic for operands of any size. It is coded with the VHDL synthetizable subset for the Synopsys/sup TM/ Behavioral Compiler. The performance results in terms of area and time delay for different operand sizes and technologies are presented and discussed.","PeriodicalId":141392,"journal":{"name":"ICECS 2001. 8th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.01EX483)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-09-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124538281","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
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