A parallel 3D DCT architecture for the compression of integral 3D images

A new VLSI architecture for the computation of the three-dimensional discrete cosine transform (3D DCT) for compression of integral 3D images is proposed. The 3D DCT is decomposed into 1D DCTs computed in each of the three dimensions. The architecture is a parallel structure which computes an N/spl times/N/spl times/N-point DCT by computing N N/spl times/N 2D DCTs in parallel and feeding each of the computed 2D DCT coefficients into a final ID DCT block. The architecture uses 5N/sup 2//2 multiplier-accumulators to evaluate N/spl times/N/spl times/N-point DCT's at a rate of N complete 3D DCT coefficients per clock cycles, where N is even. The architecture is regular and modular and as such it is suitable for VLSI implementation. The proposed architecture has a better area-time performance than previously reported 3D DCT architectures. Also, the proposed architecture reduces the initial delay by a factor of N.