用于DSP应用的除法器-乘法器高级合成库元件

ICECS 2001. 8th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.01EX483) Pub Date : 2001-09-02 DOI:10.1109/ICECS.2001.957801

M. V. R. Biarge, M. A. Sacristán, A. Álvarez, A. Diaz, V. Peinado, P. Gómez

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引用次数: 1

摘要

本文提出了一种可复用的除法器库单元。除法是通过基于连续乘法的算法来实现的。得到的结构使用定点格式，对任意大小的操作数使用二进制补码算法。它是编码与VHDL合成子集为Synopsys/sup TM/行为编译器。给出并讨论了在不同操作数大小和技术条件下的面积和时延性能结果。

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A divider-multiplier high level synthesis library element for DSP applications

In this paper a divider-multiplier reusable library cell is presented. The division is implemented by means of an algorithm based on successive multiplications. The resulting structure uses a fixed-point format and two's complement arithmetic for operands of any size. It is coded with the VHDL synthetizable subset for the Synopsys/sup TM/ Behavioral Compiler. The performance results in terms of area and time delay for different operand sizes and technologies are presented and discussed.

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ICECS 2001. 8th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.01EX483)

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