Layout design on multi-finger MOSFET for on-chip ESD protection circuits in a 0.18-/spl mu/m salicided CMOS process

Abstract

The layout design to improve uniform ESD current distribution in multi-finger MOSFET devices for better ESD robustness is investigated in a 0.18- /spl mu/m salicided CMOS process. The multi-finger MOSFET, without adding the pick-up guard ring inserted into its source region, or with the vertical direction of power line connection, can sustain a higher ESD level. The layout of I/O cell can be drawn more compactly, but is still able to provide deep-submicron CMOS ICs with higher ESD robustness.