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ICECS 2001. 8th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.01EX483)最新文献

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Second order MASH /spl utri//spl Sigma/FDM-solution with adaptive improvements 具有自适应改进的二阶MASH /spl tri//spl Sigma/ fdm解决方案
ICECS 2001. 8th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.01EX483) Pub Date : 2001-09-02 DOI: 10.1109/ICECS.2001.957652
Monica Finsrud, M. Høvin, T. Lande
{"title":"Second order MASH /spl utri//spl Sigma/FDM-solution with adaptive improvements","authors":"Monica Finsrud, M. Høvin, T. Lande","doi":"10.1109/ICECS.2001.957652","DOIUrl":"https://doi.org/10.1109/ICECS.2001.957652","url":null,"abstract":"This paper presents a new, adaptive improvement to a novel second order frequency-to-digital cascaded delta sigma modulator. The adaptive corrections significantly reduce the sensitivity to analog imperfections in the MASH-like /spl utri//spl Sigma/ frequency-to-digital modulator (/spl utri//spl Sigma/FDM), and makes it possible to implement the circuit in standard digital CMOS without loosing performance. The result is a simple second order delta-sigma modulator with high precision. Simulations of the circuit with errors and corrections are included to confirm the theory.","PeriodicalId":141392,"journal":{"name":"ICECS 2001. 8th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.01EX483)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-09-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124629098","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Distributed evolutionary design of constant-coefficient multipliers 常系数乘法器的分布式进化设计
ICECS 2001. 8th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.01EX483) Pub Date : 2001-09-02 DOI: 10.1109/ICECS.2001.957727
D. Chen, T. Aoki, N. Homma, T. Higuchi
{"title":"Distributed evolutionary design of constant-coefficient multipliers","authors":"D. Chen, T. Aoki, N. Homma, T. Higuchi","doi":"10.1109/ICECS.2001.957727","DOIUrl":"https://doi.org/10.1109/ICECS.2001.957727","url":null,"abstract":"A parallel version of the evolutionary graph generation (EGG) system, called the distributed EGG (DEGG) system, was developed on a cluster of PCs using a message-passing interface (MPI). To demonstrate the capability of DEGG, it is applied to seeking the optimal design of various multipliers. Experimental results substantially show that DEGG consistently performs better than the EGG and known conventional designs.","PeriodicalId":141392,"journal":{"name":"ICECS 2001. 8th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.01EX483)","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-09-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124659512","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Programmable current mode circuits 可编程电流模式电路
ICECS 2001. 8th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.01EX483) Pub Date : 2001-09-02 DOI: 10.1109/ICECS.2001.957536
A. Mazurek, K. Wawryn
{"title":"Programmable current mode circuits","authors":"A. Mazurek, K. Wawryn","doi":"10.1109/ICECS.2001.957536","DOIUrl":"https://doi.org/10.1109/ICECS.2001.957536","url":null,"abstract":"The paper presents a new concept of switched transconductor (ST) circuits based on the application of operational amplifiers with adjustable transconductance. It is proved that in the delay circuits proposed, one can electronically adjust its amplification, which was not possible with SI 1st and 2nd generation circuits. For the purpose of verification of the concept, a simple adjustable transconductance amplifier was designed. Simulations of delay circuits were carried out to prove the legitimacy of the concept.","PeriodicalId":141392,"journal":{"name":"ICECS 2001. 8th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.01EX483)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-09-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130912060","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
Power management systems on silicon for portable equipment 便携式设备用硅基电源管理系统
ICECS 2001. 8th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.01EX483) Pub Date : 2001-09-02 DOI: 10.1109/ICECS.2001.957648
M. Paparo
{"title":"Power management systems on silicon for portable equipment","authors":"M. Paparo","doi":"10.1109/ICECS.2001.957648","DOIUrl":"https://doi.org/10.1109/ICECS.2001.957648","url":null,"abstract":"In an application field where size, weight and battery duration often make the most relevant differentiation factors for the consumer, the paper gives a brief market overview of portable equipment, highlighting the integrated power management feature trends tied to the batteries, LCD technology evolution and increasing distributed power demand. Some examples of power management systems and battery charger topologies, underlining the possibilities offered by integrated mixed-mode technology evolution, are discussed. Finally, new possibilities offered by innovative packaging technologies that will help in further cost and size optimization are analyzed.","PeriodicalId":141392,"journal":{"name":"ICECS 2001. 8th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.01EX483)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-09-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130949849","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
High data rate synchronizers operating at low speed 以低速运行的高数据速率同步器
ICECS 2001. 8th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.01EX483) Pub Date : 2001-09-02 DOI: 10.1109/ICECS.2001.957414
A. Reis, J. F. Rocha, A. Gameiro, J. P. Carvalho
{"title":"High data rate synchronizers operating at low speed","authors":"A. Reis, J. F. Rocha, A. Gameiro, J. P. Carvalho","doi":"10.1109/ICECS.2001.957414","DOIUrl":"https://doi.org/10.1109/ICECS.2001.957414","url":null,"abstract":"This paper presents a new technique which allows high baud rate with low operation speed of the synchronizer. This technique is based on parallel processing. What is done by only one clock operating at the baud rate can be done by two clocks operating only at half rate. By generalizing we propose versions of clock recovery circuits operating at the ratio 1/2/sup n/ of the data rate. Thus we obtain circuits transmitting at very high data rate but operating at very low frequency. The proposed circuits which are transition sensitive (digital) are compared with the traditional level sensitive (analog).","PeriodicalId":141392,"journal":{"name":"ICECS 2001. 8th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.01EX483)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-09-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125642964","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 1.5 V CMOS square-root domain filter 一个1.5 V CMOS平方根域滤波器
ICECS 2001. 8th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.01EX483) Pub Date : 2001-09-02 DOI: 10.1109/ICECS.2001.957491
A. López-Martín, A. Carlosena
{"title":"A 1.5 V CMOS square-root domain filter","authors":"A. López-Martín, A. Carlosena","doi":"10.1109/ICECS.2001.957491","DOIUrl":"https://doi.org/10.1109/ICECS.2001.957491","url":null,"abstract":"A first-order CMOS integrated filter based on MOS translinear techniques is presented. The internal voltage swing compression due to its companding nature, together with the biasing scheme employed for the MOS translinear loops required, allows to operate it at supply voltages as low as one V/sub GS/ plus two V/sub DS/ of a saturated MOSFET. Measurement results demonstrate on silicon the proposed techniques, which can be readily extended to higher-order filters.","PeriodicalId":141392,"journal":{"name":"ICECS 2001. 8th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.01EX483)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-09-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121835663","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
A comparative study of digital /spl Sigma//spl Delta/ modulators for fractional-N synthesis 用于分数氮合成的数字/spl Sigma//spl Delta/调制器的比较研究
ICECS 2001. 8th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.01EX483) Pub Date : 2001-09-02 DOI: 10.1109/ICECS.2001.957474
Keliu Shu, E. Sánchez-Sinencio, F. Maloberti, U. Eduri
{"title":"A comparative study of digital /spl Sigma//spl Delta/ modulators for fractional-N synthesis","authors":"Keliu Shu, E. Sánchez-Sinencio, F. Maloberti, U. Eduri","doi":"10.1109/ICECS.2001.957474","DOIUrl":"https://doi.org/10.1109/ICECS.2001.957474","url":null,"abstract":"This paper investigates the design of digital /spl Sigma//spl Delta/ modulator (SDM) for fractional-N frequency synthesis. The design considerations are presented. Characteristics of digital /spl Sigma//spl Delta/ modulators compared with their analog counterparts are addressed. Simulation results of 4 types of digital SDMs are presented. The pros and cons of each topology are discussed in detail. Design guidelines of digital SDMs for fractional-N synthesizers are given by this comparative study.","PeriodicalId":141392,"journal":{"name":"ICECS 2001. 8th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.01EX483)","volume":"395 ","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-09-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120976228","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 25
New iterative algorithms and architectures of modular multiplication for cryptography 用于密码学的模乘法的新迭代算法和架构
ICECS 2001. 8th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.01EX483) Pub Date : 2001-09-02 DOI: 10.1109/ICECS.2001.957614
O. Nibouche, A. Bouridane, M. Nibouche
{"title":"New iterative algorithms and architectures of modular multiplication for cryptography","authors":"O. Nibouche, A. Bouridane, M. Nibouche","doi":"10.1109/ICECS.2001.957614","DOIUrl":"https://doi.org/10.1109/ICECS.2001.957614","url":null,"abstract":"Algorithms and architectures for performing modular multiplication operations, which is central to crypto-system and authentication schemes, are important in today's needs of secure communications. This paper presents two new iterative algorithms for modular multiplication. The implementation of these algorithms yields to scalable architectures that can be used for any modulus without altering the design. In addition, the Radix-2 algorithm shows almost similar features when compared with similar architectures available in the literature. Furthermore, the radix-4 algorithm can be used to develop higher radix algorithms since it only requires the use of powers of two of the modulus.","PeriodicalId":141392,"journal":{"name":"ICECS 2001. 8th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.01EX483)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-09-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121113398","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
A declarative framework for developing parametrised hardware libraries 用于开发参数化硬件库的声明式框架
ICECS 2001. 8th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.01EX483) Pub Date : 2001-09-02 DOI: 10.1109/ICECS.2001.957532
S. McKeever, W. Luk
{"title":"A declarative framework for developing parametrised hardware libraries","authors":"S. McKeever, W. Luk","doi":"10.1109/ICECS.2001.957532","DOIUrl":"https://doi.org/10.1109/ICECS.2001.957532","url":null,"abstract":"This paper describes a framework for producing pararmetrised hardware libraries based on Pebble, a simple declarative language. A family of languages based on Pebble are presented that span various levels of abstraction, from higher-order polymorphic descriptions to flattened netlists. We discuss the mechanisms, such as pass separation, that relate descriptions at different levels of abstraction, and indicate how these mechanisms provide an infrastructure in which correctness of design and design tools can be established.","PeriodicalId":141392,"journal":{"name":"ICECS 2001. 8th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.01EX483)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-09-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121237766","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
A combinatorial generalization of the Stirling Numbers of the second kind 第二类斯特林数的组合推广
ICECS 2001. 8th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.01EX483) Pub Date : 2001-09-02 DOI: 10.1109/ICECS.2001.957546
B. Cernuschi-Frías
{"title":"A combinatorial generalization of the Stirling Numbers of the second kind","authors":"B. Cernuschi-Frías","doi":"10.1109/ICECS.2001.957546","DOIUrl":"https://doi.org/10.1109/ICECS.2001.957546","url":null,"abstract":"A combinatorial generalization of the Stirling Numbers of the second kind is presented as the number of partitions of a set with n elements in m subsets with at least c elements each. An equivalence with a previous definition is discussed. Combinatorial properties and a recursive relation are obtained. The generating function is obtained as the m-th power of a truncated exponential series expansion at c. Other applications are also discussed.","PeriodicalId":141392,"journal":{"name":"ICECS 2001. 8th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.01EX483)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-09-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116373744","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
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