{"title":"一个1.5 V CMOS平方根域滤波器","authors":"A. López-Martín, A. Carlosena","doi":"10.1109/ICECS.2001.957491","DOIUrl":null,"url":null,"abstract":"A first-order CMOS integrated filter based on MOS translinear techniques is presented. The internal voltage swing compression due to its companding nature, together with the biasing scheme employed for the MOS translinear loops required, allows to operate it at supply voltages as low as one V/sub GS/ plus two V/sub DS/ of a saturated MOSFET. Measurement results demonstrate on silicon the proposed techniques, which can be readily extended to higher-order filters.","PeriodicalId":141392,"journal":{"name":"ICECS 2001. 8th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.01EX483)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2001-09-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"5","resultStr":"{\"title\":\"A 1.5 V CMOS square-root domain filter\",\"authors\":\"A. López-Martín, A. Carlosena\",\"doi\":\"10.1109/ICECS.2001.957491\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A first-order CMOS integrated filter based on MOS translinear techniques is presented. The internal voltage swing compression due to its companding nature, together with the biasing scheme employed for the MOS translinear loops required, allows to operate it at supply voltages as low as one V/sub GS/ plus two V/sub DS/ of a saturated MOSFET. Measurement results demonstrate on silicon the proposed techniques, which can be readily extended to higher-order filters.\",\"PeriodicalId\":141392,\"journal\":{\"name\":\"ICECS 2001. 8th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.01EX483)\",\"volume\":\"17 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2001-09-02\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"5\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"ICECS 2001. 8th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.01EX483)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICECS.2001.957491\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"ICECS 2001. 8th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.01EX483)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICECS.2001.957491","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A first-order CMOS integrated filter based on MOS translinear techniques is presented. The internal voltage swing compression due to its companding nature, together with the biasing scheme employed for the MOS translinear loops required, allows to operate it at supply voltages as low as one V/sub GS/ plus two V/sub DS/ of a saturated MOSFET. Measurement results demonstrate on silicon the proposed techniques, which can be readily extended to higher-order filters.