A 1.5 V CMOS square-root domain filter

Abstract

A first-order CMOS integrated filter based on MOS translinear techniques is presented. The internal voltage swing compression due to its companding nature, together with the biasing scheme employed for the MOS translinear loops required, allows to operate it at supply voltages as low as one V/sub GS/ plus two V/sub DS/ of a saturated MOSFET. Measurement results demonstrate on silicon the proposed techniques, which can be readily extended to higher-order filters.