一个1.2 V 500 MHz 32位超前进位加法器

ICECS 2001. 8th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.01EX483) Pub Date : 2001-09-02 DOI:10.1109/ICECS.2001.957587

Kuo-Hsing Cheng, Wen-Shiuan Lee, Yung-Chong Huang

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引用次数: 6

摘要

本文提出了一种适用于高速、低电压应用的1.2 V 32位进位前置加法器。所提出的新32位加法器使用非全摆压真单相时钟逻辑(NSTSPC)来实现所提出的进位前置加法器。由于NSTSPC的内部节点为非满摆状态，其运算速度将高于传统的TSPC。此外，新加法器的电源电压为1.2 V，因此功耗也会降低。采用0.35 /spl mu/m 1P4M CMOS技术，1.2 V电源的32位CLA加法器可在500 MHz时钟频率下工作。

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A 1.2 V 500 MHz 32-bit carry-lookahead adder

In this paper a 1.2 V 32-bit carry lookahead adder is proposed for high speed, low voltage applications. The proposed new 32-bit adder uses Non-full Voltage Swing True-Single-Phase-Clocking Logic (NSTSPC) to implement the proposed carry lookahead adder. Because the internal node of NSTSPC was non-full swing, its operation speed would be higher than the conventional TSPC. Moreover, the supply voltage for the new adder is 1.2 V, thus the power dissipation would also be reduced. The 32-bit CLA adder using 0.35 /spl mu/m 1P4M CMOS technology with 1.2 V power supply could be operated at a 500 MHz clock frequency.

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ICECS 2001. 8th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.01EX483)

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