Five new high-performance multiplexer-based 1-bit full adder cells

Abstract

Five new multiplexer-based architectures for 1-bit full adder cell design are presented. Implementing with the pass-gate CMOS multiplexer, results in five distinct adders. Those adder cells along with the conventional 28-transistor CMOS adder are tested using H-Spice under 6 different frequencies and 6 different loads. Testing results shows the new cells exhibit on average 21.7% increase in sum signal speed, and 19.9% increase in carry out signal speed over the conventional 28-transistor CMOS adder, with power-delay product savings reaching up to 18.4%.