Multirate digital squarer architectures

Abstract

By using multirate signal processing, we propose interleaved and pipelined architectures for digital squarers. The hardware implementation of the proposed architectures and their complexity are discussed at the gate level. In comparison to a recently proposed divide-and-conquer squarer architecture, and for the same throughput, our squarer's hardware complexity is approximately 15% less for a 16-bit squarer, and 23% less for a 32-bit squarer.