五个新的高性能基于多路复用器的1位全加法器单元

ICECS 2001. 8th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.01EX483) Pub Date : 2001-09-02 DOI:10.1109/ICECS.2001.957597

A. Al-Sheraidah, B. Alhalabi, H. Bui

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引用次数: 3

摘要

提出了五种新的基于多路复用器的1位全加法器单元设计架构。用通栅CMOS多路复用器实现，结果有五个不同的加法器。这些加法器单元以及传统的28晶体管CMOS加法器在6种不同频率和6种不同负载下使用H-Spice进行了测试。测试结果表明，与传统的28晶体管CMOS加器相比，新单元的和信号速度平均提高21.7%，执行信号速度平均提高19.9%，功率延迟产品节省高达18.4%。

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Five new high-performance multiplexer-based 1-bit full adder cells

Five new multiplexer-based architectures for 1-bit full adder cell design are presented. Implementing with the pass-gate CMOS multiplexer, results in five distinct adders. Those adder cells along with the conventional 28-transistor CMOS adder are tested using H-Spice under 6 different frequencies and 6 different loads. Testing results shows the new cells exhibit on average 21.7% increase in sum signal speed, and 19.9% increase in carry out signal speed over the conventional 28-transistor CMOS adder, with power-delay product savings reaching up to 18.4%.

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ICECS 2001. 8th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.01EX483)

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