2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)最新文献_第8页

A Multi-accuracy-Level Approximate Memory Architecture Based on Data Significance Analysis 基于数据显著性分析的多精度级近似存储体系结构

2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2016-07-01 DOI: 10.1109/ISVLSI.2016.84

Yuanchang Chen, Xinghua Yang, F. Qiao, Jie Han, Qi Wei, Huazhong Yang

引用次数: 13

Reliable Many-Core System-on-Chip Design Using K-Node Fault Tolerant Graphs 基于k节点容错图的可靠多核片上系统设计

2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2016-07-01 DOI: 10.1109/ISVLSI.2016.40

Z. Wang, Alessandro Littarru, E. Ugwu, Shazia Kanwal, A. Chattopadhyay

引用次数: 1

A Design Space Exploration Methodology for Parameter Optimization in Multicore Processors 多核处理器参数优化的设计空间探索方法

2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2016-07-01 DOI: 10.1109/ISVLSI.2016.92

Prasanna Kansakar, Arslan Munir

{"title":"A Design Space Exploration Methodology for Parameter Optimization in Multicore Processors","authors":"Prasanna Kansakar, Arslan Munir","doi":"10.1109/ISVLSI.2016.92","DOIUrl":"https://doi.org/10.1109/ISVLSI.2016.92","url":null,"abstract":"Due to the increasing proliferation of computing systems in diverse application domains, the need for application-specific design of multicore/manycore processing platforms is paramount. In order to tailor processors for application-specific requirements, a multitude of processor design parameters need to be tuned accordingly. Tuning of processor design parameters involves rigorous and extensive design space exploration over large search spaces. In this paper, we propose an efficient design space exploration methodology for multicore parameter optimization. Our proposed methodology includes an intelligent initial parameter setting algorithm, the results of which are leveraged by two search algorithms-exhaustive search and greedy search. We evaluate the methodology in a cycle-accurate simulator (ESESC) using standard set of PARSEC and SPLASH2 benchmarks for applications with low-power and highperformance requirements. The results reveal that the quality of solutions (design configurations) obtained from our methodology are within 1.35%-3.69% of the solutions obtained from fully exhaustive search while only exploring 2.74%-3% of the design space. Our methodology achieves on average a 35.32× speedup in design space exploration time as compared to fully exhaustive search in finding the best processor design configuration.","PeriodicalId":140647,"journal":{"name":"2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)","volume":"76 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123474027","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Analysis of Switching Energy and Delay for Magnetic Logic Devices 磁逻辑器件的开关能量和延时分析

2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2016-07-01 DOI: 10.1109/ISVLSI.2016.17

M. Rao, Neha Oraon

{"title":"Analysis of Switching Energy and Delay for Magnetic Logic Devices","authors":"M. Rao, Neha Oraon","doi":"10.1109/ISVLSI.2016.17","DOIUrl":"https://doi.org/10.1109/ISVLSI.2016.17","url":null,"abstract":"Magnetic logic is considered as one of the alternate technologies to the existing CMOS engineering in designing digital logic circuits. In magnetic logic, the spin directions are considered as logic levels instead of electric charge used in CMOS modules. If magnetic dots are suitably arranged, antiferromagnetic and ferromagnetic coupling can be utilized to represent a digital circuit. In this paper, we have studied different shapes of magnetic material such as ellipsoidal, funnel, dome, d, rectangle, and pacman to determine the magnetic interplay between the input and other arranged logical dots. The logical operation is dependent on the parity and the overall assembly of dots. All the selected shapes in this study, exhibited ferromagnetic and antiferromagnetic coupling between the dots, which wasfurther employed to design inverter digital circuit. A comparative analysis in terms of switching energy, and propogation delay were investigated for inverter logic design. Among all the selected shapes, the ellipsoidal profile was best suited to develop digital circuits with respect to energy-delay product. The performance of a multiplexer circuit consisting of AND and OR logic output was investigated using ellipsoidal and rectangular shaped ferro-magnetic dots.","PeriodicalId":140647,"journal":{"name":"2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115375147","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4

Security Challenges in CPS and IoT: From End-Node to the System CPS和物联网中的安全挑战:从终端节点到系统

2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2016-07-01 DOI: 10.1109/ISVLSI.2016.109

K. Ly, Yier Jin

引用次数: 17

Multi Clock Flooded LDPC Decoding Architecture with Reduced Memory and Interconnect 具有小内存和互连的多时钟淹没LDPC译码结构

2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2016-07-01 DOI: 10.1109/ISVLSI.2016.104

O. Boncalo, Ioana Mot

引用次数: 0

A Dual-Threshold Voltage Approach for Timing Speculation in CMOS Circuits CMOS电路中时序推测的双阈值电压方法

2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2016-07-01 DOI: 10.1109/ISVLSI.2016.119

Xiaowen Wang, W. H. Robinson

{"title":"A Dual-Threshold Voltage Approach for Timing Speculation in CMOS Circuits","authors":"Xiaowen Wang, W. H. Robinson","doi":"10.1109/ISVLSI.2016.119","DOIUrl":"https://doi.org/10.1109/ISVLSI.2016.119","url":null,"abstract":"Better Than Worst-Case design is a style that aims to improve performance by breaking from traditional design practice. It allows certain timing errors to occur during the normal operation of the integrated circuit (IC), while preserving correctness by adding error detection and correction (EDAC). In order to quantify the tradeoff between the performance gain and the error rate during the design phase, an understanding is needed of: (1) how circuits behave under typical loads, and (2) what error rate is produced when the clock goes beyond the traditional limit. This paper describes a design automation flow that enables designers to obtain timing errors from analyzing value change dump files. The timing information is back-annotated into a synthesized netlist before simulation. By using circuit statistical results of the cells' switching activity, timing errors can be reduced by replacing highly active and critical cells from a low-threshold cell library. Critical cells on error-prone paths are identified based on Monte Carlo simulations. Four different ISCAS85 circuits (i.e., multiplier, ALU, SEC/DED, and interrupt controller) were selected and synthesized with the Synopsys 32-nm library. The performance improvement using the dual-threshold voltage ranged from 16% to 30% for the selected benchmark circuits.","PeriodicalId":140647,"journal":{"name":"2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127751231","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Fault-Tolerant Clock Synchronization with High Precision 高精度的容错时钟同步

2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2016-07-01 DOI: 10.1109/ISVLSI.2016.88

Attila Kinali, F. Huemer, C. Lenzen

引用次数: 8

Write Pulse Scaling for Energy Efficient STT-MRAM 高效STT-MRAM的写脉冲缩放

2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2016-07-01 DOI: 10.1109/ISVLSI.2016.118

Y. Alkabani, Zach Koopmans, Haifeng Xu, A. Jones, R. Melhem

引用次数: 7

Low-Power Wearable System for Real-Time Screening of Obstructive Sleep Apnea 用于阻塞性睡眠呼吸暂停实时筛查的低功耗可穿戴系统

2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2016-07-01 DOI: 10.1109/ISVLSI.2016.51

Grégoire Surrel, F. Rincón, S. Murali, David Atienza Alonso

{"title":"Low-Power Wearable System for Real-Time Screening of Obstructive Sleep Apnea","authors":"Grégoire Surrel, F. Rincón, S. Murali, David Atienza Alonso","doi":"10.1109/ISVLSI.2016.51","DOIUrl":"https://doi.org/10.1109/ISVLSI.2016.51","url":null,"abstract":"Obstructive Sleep Apnea (OSA) is one of the main sleep disorders, but only 10% of the cases are diagnosed. Moreover, there is a lack of tools for long-term monitoring of OSA, since current systems are too bulky and intrusive to be used continuously. In this context, recent studies have shown that it is possible to detect it automatically based on single-lead ECG recordings. This approach can be used in non-invasive smart wearable sensors which measure and process bio-signals online. This work focuses on the implementation, optimization and integration of an algorithm for OSA detection for preventive health-care. It relies on a frequency-domain analysis while targeting an ultra-low power embedded wearable device. As it must share its resources usage with other computations, it must be as lightweight as possible. Our current results based on publicly available signals show a classification accuracy of up to 83.2% for both the offline analysis and the embedded online one. This system gives an even better classification accuracy than the best offline algorithm when using the same features for classification [1].","PeriodicalId":140647,"journal":{"name":"2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122764676","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 9