A Dual-Threshold Voltage Approach for Timing Speculation in CMOS Circuits

Abstract

Better Than Worst-Case design is a style that aims to improve performance by breaking from traditional design practice. It allows certain timing errors to occur during the normal operation of the integrated circuit (IC), while preserving correctness by adding error detection and correction (EDAC). In order to quantify the tradeoff between the performance gain and the error rate during the design phase, an understanding is needed of: (1) how circuits behave under typical loads, and (2) what error rate is produced when the clock goes beyond the traditional limit. This paper describes a design automation flow that enables designers to obtain timing errors from analyzing value change dump files. The timing information is back-annotated into a synthesized netlist before simulation. By using circuit statistical results of the cells' switching activity, timing errors can be reduced by replacing highly active and critical cells from a low-threshold cell library. Critical cells on error-prone paths are identified based on Monte Carlo simulations. Four different ISCAS85 circuits (i.e., multiplier, ALU, SEC/DED, and interrupt controller) were selected and synthesized with the Synopsys 32-nm library. The performance improvement using the dual-threshold voltage ranged from 16% to 30% for the selected benchmark circuits.