2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)最新文献

High-Accuracy FIR Filter Design Using Stochastic Computing 基于随机计算的高精度FIR滤波器设计

2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2016-09-08 DOI: 10.1109/ISVLSI.2016.63

Bo Yuan, Yanzhi Wang

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引用次数: 14

An Integrated Common Gate CTLE Receiver Front End with Charge Mode Adaptation 具有电荷模式自适应的集成共门CTLE接收机前端

2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2016-07-11 DOI: 10.1109/ISVLSI.2016.105

Divya Duvvuri, V. Pasupureddi

引用次数: 1

Post-Placement Optimization for Thermal-Induced Mechanical Stress Reduction 热诱导机械应力减小的贴片后优化

2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2016-07-11 DOI: 10.1109/ISVLSI.2016.69

Tiantao Lu, Zhiyuan Yang, Ankur Srivastava

引用次数: 4

VLSI Architecture for Cyclostationary Feature Detection Based Spectrum Sensing for Cognitive-Radio Wireless Networks and Its ASIC Implementation 基于循环平稳特征检测的认知无线网络频谱感知VLSI体系结构及其ASIC实现

2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2016-07-11 DOI: 10.1109/ISVLSI.2016.12

M. S. Murty, R. Shrestha

{"title":"VLSI Architecture for Cyclostationary Feature Detection Based Spectrum Sensing for Cognitive-Radio Wireless Networks and Its ASIC Implementation","authors":"M. S. Murty, R. Shrestha","doi":"10.1109/ISVLSI.2016.12","DOIUrl":"https://doi.org/10.1109/ISVLSI.2016.12","url":null,"abstract":"Cyclostationary feature detection for spectrum sensing in cognitive radio network has significant prospect in future wireless communication systems. This work deals with the very-large scale integration(VLSI) architectural transformation of such detection algorithm for field-programmable gate-array (FPGA) prototyping and application-specific integrated-circuit (ASIC) design. System level design of this detection algorithm and the architectures of all its internal blocks has been proposed in this paper. Subsequently, performance analysis ofthe suggested detector in additive-white Gaussian-noise (AWGN) environmenthas been carried out where it could deliver 0.95 probability ofdetection at -6 dB. Similarly, performance comparison of the implementedand simulated detector showed that there is a absolute error of only 0.07. Eventually, the proposed system-level architecture is synthesized and postlayoutsimulated using 90 nm complementary metal-oxide semiconductor(CMOS) technology node. It occupies 23.13 mm2 of core area with 3663Kgate-equivalents and consumes total power of 6.5 W at 100 MHz clock frequency.","PeriodicalId":140647,"journal":{"name":"2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)","volume":"54 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-07-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129409605","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 11

Angel-Eye: A Complete Design Flow for Mapping CNN onto Customized Hardware 天使之眼:将CNN映射到定制硬件的完整设计流程

2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2016-07-11 DOI: 10.1109/ISVLSI.2016.129

Kaiyuan Guo, Lingzhi Sui, Jiantao Qiu, Song Yao, Song Han, Yu Wang, Huazhong Yang

引用次数: 54

Speeding up Incremental Legalization with Fast Queries to Multidimensional Trees 通过对多维树的快速查询加速增量合法化

2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2016-07-11 DOI: 10.1109/ISVLSI.2016.122

R. Netto, Vinicius S. Livramento, C. Guth, L. Santos, José Luís Almada Güntzel

引用次数: 1

Design Space Exploration of FinFETs with Double Fin Heights for Standard Cell Library 标准单元库双翅片高度finfet的设计空间探索

2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2016-07-11 DOI: 10.1109/ISVLSI.2016.72

Chi-Hung Lin, Chia-Shiang Chen, Yu-He Chang, Yu Ting Zhang, Shang-Rong Fang, Santanu Santra, Rung-Bin Lin

引用次数: 4

Gossip NoC -- Avoiding Timing Side-Channel Attacks through Traffic Management 八卦NoC——通过流量管理避免定时侧信道攻击

2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2016-07-11 DOI: 10.1109/ISVLSI.2016.25

C. Reinbrecht, A. Susin, L. Bossuet, Martha Johanna Sepúlveda

引用次数: 47

Efficient Low-Density Parity-Check (LDPC) Code Decoding for Combating Asymmetric Errors in STT-RAM STT-RAM中对抗非对称错误的高效低密度奇偶校验(LDPC)码解码

2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2016-07-11 DOI: 10.1109/ISVLSI.2016.9

Bohua Li, Yukui Pei, Wujie Wen

{"title":"Efficient Low-Density Parity-Check (LDPC) Code Decoding for Combating Asymmetric Errors in STT-RAM","authors":"Bohua Li, Yukui Pei, Wujie Wen","doi":"10.1109/ISVLSI.2016.9","DOIUrl":"https://doi.org/10.1109/ISVLSI.2016.9","url":null,"abstract":"Spin-transfer torque random access memory (STT-RAM) has emerged as a promising nonvolatile memory technology for its fast speed, small footprint and zero standby power. However, the unique and unusual high asymmetric error rates at different memory bit operations, which are proved to be far beyond the efficiency of common error correction codes (ECCs), greatly hinder its applications. In this work, we investigate the potentials of the powerful low-density parity-check (LDPC) code to address the aggravated reliability issue in STT-RAM. We first develop a holistic STT-RAM channel model to quantitatively measure the asymmetric effects during the write and read process for single-level-cell (SLC) and multi-level-cell (MLC) design. We then propose an asymmetric LDPC (A-LDPC) decoding to particularly enhance the asymmetric error correcting capability. An STT-RAM dedicated hardware-favorable soft information, namely asymmetric Log-Likelihood Ratio (A-LLR), is also derived from the proposed channel model. Experimental results show that our A-LDPC can outperform at least two/four orders of magnitude over existing ECCs for combating the asymmetric bit errors in SLC/MLC STT-RAM.","PeriodicalId":140647,"journal":{"name":"2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-07-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134511800","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 10

Memristor-Based Discrete Fourier Transform for Improving Performance and Energy Efficiency 基于忆阻器的离散傅里叶变换提高性能和能源效率

2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2016-07-11 DOI: 10.1109/ISVLSI.2016.124

R. Cai, Ao Ren, Yanzhi Wang, Bo Yuan

引用次数: 5