VLSI Architecture for Cyclostationary Feature Detection Based Spectrum Sensing for Cognitive-Radio Wireless Networks and Its ASIC Implementation

Cyclostationary feature detection for spectrum sensing in cognitive radio network has significant prospect in future wireless communication systems. This work deals with the very-large scale integration(VLSI) architectural transformation of such detection algorithm for field-programmable gate-array (FPGA) prototyping and application-specific integrated-circuit (ASIC) design. System level design of this detection algorithm and the architectures of all its internal blocks has been proposed in this paper. Subsequently, performance analysis ofthe suggested detector in additive-white Gaussian-noise (AWGN) environmenthas been carried out where it could deliver 0.95 probability ofdetection at -6 dB. Similarly, performance comparison of the implementedand simulated detector showed that there is a absolute error of only 0.07. Eventually, the proposed system-level architecture is synthesized and postlayoutsimulated using 90 nm complementary metal-oxide semiconductor(CMOS) technology node. It occupies 23.13 mm2 of core area with 3663Kgate-equivalents and consumes total power of 6.5 W at 100 MHz clock frequency.