2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)最新文献_第2页

Synthesizing Asynchronous Circuits toward Practical Use 面向实际应用的综合异步电路

2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2016-07-11 DOI: 10.1109/ISVLSI.2016.29

Heechun Park, Taewhan Kim

引用次数: 1

Online Unusual Behavior Detection for Temperature Sensor Networks 温度传感器网络在线异常行为检测

2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2016-07-11 DOI: 10.1109/ISVLSI.2016.120

Hengyang Zhao, S. Tan, Hai Wang, Hai-Bao Chen

{"title":"Online Unusual Behavior Detection for Temperature Sensor Networks","authors":"Hengyang Zhao, S. Tan, Hai Wang, Hai-Bao Chen","doi":"10.1109/ISVLSI.2016.120","DOIUrl":"https://doi.org/10.1109/ISVLSI.2016.120","url":null,"abstract":"In modern smart building climate control systems, accurate detection of unusual behavior in temperature sensors (outliers) can help reduce or prevent waste of energy consumption in a Heating, Ventilation and Air Conditioning (HVAC) system. In this work, we propose online learning-distance based outlier detection method. In the new method, we train and tune a multilayer neural network to learn a nonlinear distance function from historical building operation data and detect outliers according to the calculated distance. The online detection method is less computational expensive than the offline version. By gradually including new and drop old building operation record, the new method is capable to adjust the underlying distance function on-the-fly. The converging speed of the learned distance function and tuning difficulty of network training are also discussed. The proposed online outlier detection method can work in an unsupervised manner except requiring only one data-specific parameter. In the experiments of two simulated buildings, the data-specific parameter can be chosen from a relatively wide range, which allows less tuning effort, to achieve good online detection precision and recall.","PeriodicalId":140647,"journal":{"name":"2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-07-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130319125","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A Comparative Study of Si/Ge and GaSb/InAs Tunnel FET-Based Cellular Neural Network 基于Si/Ge和GaSb/InAs隧道场效应效应的细胞神经网络比较研究

2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2016-07-11 DOI: 10.1109/ISVLSI.2016.39

A. Trivedi, Susmita Dey Manasi

{"title":"A Comparative Study of Si/Ge and GaSb/InAs Tunnel FET-Based Cellular Neural Network","authors":"A. Trivedi, Susmita Dey Manasi","doi":"10.1109/ISVLSI.2016.39","DOIUrl":"https://doi.org/10.1109/ISVLSI.2016.39","url":null,"abstract":"This work presents a comparative analysis of Si/Ge and GaSb/InAs heterojunction Tunnel FET (TFET)-based cellular neural networks (CNNs). TFET-based CNNs are also compared against an equivalent FinFET-based CNN. A simulation methodology is shown to project realistic estimation of TFET-CNN performance based on the measured IDS-VGS characteristics of TFETs. III-V-TFET (i.e., GaSb/InAs TFET) shows a higher performance in CNN than Si/Ge-TFET due to a higher ON-current and much steeper switching slope (SS) in III-V-TFET. Meanwhile, Si/Ge-TFET shows a much lower OFF-current than III-V-TFET, and it is more suitable for ultralow power CNN applications. Cohesive simulation methodology discussed in the work also identifies that suppression of trap-assisted-tunneling (TAT)-induced leakage is critical to enable energy efficient TFET-based CNN. While a higher gate-to-drain capacitance (CGD, Miller capacitance) becomes a challenge in TFET-based digital designs, suitable design techniques are described to suppress its implications in throughput efficiency of TFET-CNN. Application of TFET-CNN is considered for image processing. Power-performance characteristics of CNN designs based on both the TFETs are compared.","PeriodicalId":140647,"journal":{"name":"2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)","volume":"309 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-07-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134562667","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Energy-Efficient and Secure S-Box Circuit Using Symmetric Pass Gate Adiabatic Logic 采用对称通门绝热逻辑的节能安全s盒电路

2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2016-07-11 DOI: 10.1109/ISVLSI.2016.45

S. D. Kumar, H. Thapliyal, Azhar Mohammad, Vijay Singh, K. Perumalla

{"title":"Energy-Efficient and Secure S-Box Circuit Using Symmetric Pass Gate Adiabatic Logic","authors":"S. D. Kumar, H. Thapliyal, Azhar Mohammad, Vijay Singh, K. Perumalla","doi":"10.1109/ISVLSI.2016.45","DOIUrl":"https://doi.org/10.1109/ISVLSI.2016.45","url":null,"abstract":"Differential Power Analysis (DPA) attack is considered to be a main threat while designing cryptographic processors. In cryptographic algorithms like DES and AES, S-Box is used to indeterminate the relationship between the keys and the cipher texts. However, S-box is prone to DPA attack due to its high power consumption. In this paper, we are implementing an energy-efficient 8-bit S-Box circuit using our proposed Symmetric Pass Gate Adiabatic Logic (SPGAL). SPGAL is energy-efficient as compared to the existing DPA-resistant adiabatic and non-adiabatic logic families. SPGAL is energy-efficient due to reduction of non-adiabatic loss during the evaluate phase of the outputs. Further, the S-Box circuit implemented using SPGAL is resistant to DPA attacks. The results are verified through SPICE simulations in 180nm technology. SPICE simulations show that the SPGAL based S-Box circuit saves upto 92% and 67% of energy as compared to the conventional CMOS and Secured Quasi-Adiabatic Logic (SQAL) based S-Box circuit. From the simulation results, it is evident that the SPGAL based circuits are energy-efficient as compared to the existing DPA-resistant adiabatic and non-adiabatic logic families. In nutshell, SPGAL based gates can be used to build secure hardware for low power portable electronic devices and Internet-of-Things (IoT) based electronic devices.","PeriodicalId":140647,"journal":{"name":"2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)","volume":"62 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-07-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114868278","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 15

On the Design of Ultra-High Density 14nm Finfet Based Transistor-Level Monolithic 3D ICs 超高密度14nm晶体管级单片3D集成电路设计

2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2016-07-11 DOI: 10.1109/ISVLSI.2016.94

Jiajun Shi, D. Nayak, M. Ichihashi, S. Banna, C. A. Moritz

引用次数: 20

Hardware Trust through Layout Filling: A Hardware Trojan Prevention Technique 基于布局填充的硬件信任:一种硬件防木马技术

2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2016-07-11 DOI: 10.1109/ISVLSI.2016.22

Papa-Sidi Ba, Sophie Dupuis, P. Manikandan, M. Flottes, G. D. Natale, B. Rouzeyre

引用次数: 21

Timing Analysis and Optimization Based on Flexible Flip-Flop Timing Model 基于柔性触发器时序模型的时序分析与优化

2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2016-07-11 DOI: 10.1109/ISVLSI.2016.41

Jeongwoo Heo, Taewhan Kim

引用次数: 2

Next Generation Automotive Architecture Modeling and Exploration for Autonomous Driving 面向自动驾驶的下一代汽车架构建模与探索

2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2016-07-11 DOI: 10.1109/ISVLSI.2016.126

Bowen Zheng, Hengyi Liang, Qi Zhu, Huafeng Yu, Chung-Wei Lin

引用次数: 21

A 90-nm CMOS Frequency Synthesizer with a Tripler for 60-GHz Wireless Communication Systems 一种用于60 ghz无线通信系统的带有三倍器的90纳米CMOS频率合成器

2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2016-07-11 DOI: 10.1109/ISVLSI.2016.37

Po-Tsang Chen, Ching-Yuan Yang

引用次数: 0

A VLSI Design for Neuromorphic Computing 神经形态计算的VLSI设计

2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2016-07-11 DOI: 10.1109/ISVLSI.2016.81

Mark E. Dean, Christopher Daffron

引用次数: 11