2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)最新文献_第3页

Hardware Design Automation of Convolutional Neural Networks 卷积神经网络的硬件设计自动化

2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2016-07-11 DOI: 10.1109/ISVLSI.2016.101

Andrea Solazzo, Emanuele Del Sozzo, Irene De Rose, M. Silvestri, Gianluca Durelli, M. Santambrogio

{"title":"Hardware Design Automation of Convolutional Neural Networks","authors":"Andrea Solazzo, Emanuele Del Sozzo, Irene De Rose, M. Silvestri, Gianluca Durelli, M. Santambrogio","doi":"10.1109/ISVLSI.2016.101","DOIUrl":"https://doi.org/10.1109/ISVLSI.2016.101","url":null,"abstract":"Convolutional Neural Networks (CNNs) are a variation of feed-forward Neural Networks inspired by the biological process in the visual cortex of animals. The interest in this supervised learning algorithm has rapidly grown in many fields like image and video recognition and natural language processing. Nowadays they have become the state of the art in various applications like mobile robot vision, video surveillance and Big Data analytics. The specific computation pattern of CNNs results to be highly suitable for hardware acceleration, in fact different types of accelerators have been proposed based on GPU, Field Programmable Gate Array (FPGA) and ASIC. In particular, in the embedded systems context, due to real time and power consumption challenges, it is crucial to find the right tradeoff between performance, energy efficiency, fast development round and cost. This work proposes a framework meant as a tool for the user to accelerate and simplify the design and the implementation of CNNs on FPGAs by leveraging High Level Synthesis, still providing a certain level of customization of the hardware design.","PeriodicalId":140647,"journal":{"name":"2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-07-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114669830","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 9

FPGA Based Cyber Security Protocol for Automated Traffic Monitoring Systems: Proposal and Implementation 基于FPGA的自动交通监控系统网络安全协议:建议与实现

2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2016-07-11 DOI: 10.1109/ISVLSI.2016.97

A. Chattopadhyay, V. Pudi, Anubhab Baksi, T. Srikanthan

{"title":"FPGA Based Cyber Security Protocol for Automated Traffic Monitoring Systems: Proposal and Implementation","authors":"A. Chattopadhyay, V. Pudi, Anubhab Baksi, T. Srikanthan","doi":"10.1109/ISVLSI.2016.97","DOIUrl":"https://doi.org/10.1109/ISVLSI.2016.97","url":null,"abstract":"There is a rapidly growing interest in the field of unmanned road vehicles across the world. To aid the traffic management of such systems, there is an urgent need to develop appropriate security protocols facilitating car-to-car and car-to-traffic controller systems. Ensuring security requires both confidentiality (will be understandable only to intended recipients) as well as authenticity (message is not tampered during communication), both of which are taken care of in an Authenticated Encryption with Associated Data (AEAD) scheme. In this paper, we propose a new AEAD-based protocol for secure and authenticated transmission of videos to the base station captured by traffic monitoring systems in real time. Our protocol utilizes ACORN v2, a lightweight AEAD primitive. For the secret key to be used in encryption-authentication, we use the concept of Physically Unclonable Functions (PUFs). The entire protocol is implemented and evaluated with an FPGA-based prototype, using a 640x480 pixel camera with 30 frames per second. The area required for the proposed protocol is 5% of the total FPGA device (Xilinx Zynq-XC7Z020-1clg484).","PeriodicalId":140647,"journal":{"name":"2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-07-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128124944","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 5

A Memristor Crossbar Based Computing Engine Optimized for High Speed and Accuracy 一种基于忆阻器横条的高速高精度计算引擎

2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2016-07-11 DOI: 10.1109/ISVLSI.2016.46

Chenchen Liu, Qing Yang, Bonan Yan, Jianlei Yang, Xiaocong Du, Weijie Zhu, Hao Jiang, Qing Wu, Mark D. Barnell, Hai Helen Li

{"title":"A Memristor Crossbar Based Computing Engine Optimized for High Speed and Accuracy","authors":"Chenchen Liu, Qing Yang, Bonan Yan, Jianlei Yang, Xiaocong Du, Weijie Zhu, Hao Jiang, Qing Wu, Mark D. Barnell, Hai Helen Li","doi":"10.1109/ISVLSI.2016.46","DOIUrl":"https://doi.org/10.1109/ISVLSI.2016.46","url":null,"abstract":"Matrix-vector multiplication, as a key computing operation, has been largely adopted in applications and hence greatly affects the execution efficiency. A common technique to enhance the performance of matrix-vector multiplication is increasing execution parallelism, which results in higher design cost. In recent years, new devices and structures have been widely investigated as alternative solutions. Among them, memristor crossbar demonstrates a great potential for its intrinsic support of matrix-vector multiplication, high integration density, and built-in parallel execution. However, the computation accuracy and speed of such designs are limited and constrained by the features of crossbar array and peripheral circuitry. In this work, we propose a new memristor crossbar based computing engine design by leveraging a current sensing scheme. High operation parallelism and therefore fast computation can be achieved by simultaneously supplying analog voltages into a memristor crossbar and directly detecting weighted currents through current amplifiers. The performance and effectiveness of the proposed design were examined through the implementation of a neural network for pattern recognition based on MNIST database. Compared to a prior reported design, ours increases the recognition accuracy 8.1% (to 94.6%).","PeriodicalId":140647,"journal":{"name":"2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)","volume":"114 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-07-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133247374","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 38

Attacking an SRAM-Based PUF through Wearout 通过磨损攻击基于sram的PUF

2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2016-07-11 DOI: 10.1109/ISVLSI.2016.68

A. Roelke, M. Stan

引用次数: 20

A New Process Variation Monitoring Circuit 一种新型工艺变化监测电路

2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2016-07-11 DOI: 10.1109/ISVLSI.2016.26

D. Mirzoyan, Ararat Khachatryan

{"title":"A New Process Variation Monitoring Circuit","authors":"D. Mirzoyan, Ararat Khachatryan","doi":"10.1109/ISVLSI.2016.26","DOIUrl":"https://doi.org/10.1109/ISVLSI.2016.26","url":null,"abstract":"A new process variation monitoring circuit (PVMC) has been proposed in the paper. The goal is to generate a digital signal/code which (code value) will characterize the process corner. The circuit uses only metal-oxide-semiconductor (MOS) transistors to detect variation of their parameters, or process corner by generating digital signals. Process variation is detected based on variation of parameters of n-type MOS transistor, such as threshold voltage, oxide thickness. Proposed circuits' operation is based on a method called “dynamic measurement”, which enables to monitor process variation or corner by using only one type of transistors (n-type or p-type). Absence of devices such as bipolar transistors, diodes and resistors, reference voltage or current (or other parameters) sources leads to increase in detection accuracy and simplicity, as well as circuit area and current reduction. Post-layout simulation results prove correct functionality of the proposed circuit. Although proposed circuit detects process variation/corner by dealing with parameters of n-type MOS transistors, it can be easily modified to include/detect variation of also p-type MOS transistors, resistors or other components.","PeriodicalId":140647,"journal":{"name":"2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)","volume":"64 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-07-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132646529","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

A Configurable and Lightweight Timing Monitor for Fault Attack Detection 用于故障攻击检测的可配置轻量级定时监视器

2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2016-07-11 DOI: 10.1109/ISVLSI.2016.123

Chinmay Deshpande, Bilgiday Yuce, N. F. Ghalaty, D. Ganta, P. Schaumont, L. Nazhandali

引用次数: 11

Adaptive Overclocking and Error Correction Based on Dynamic Speculation Window 基于动态推测窗口的自适应超频与纠错

2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2016-07-11 DOI: 10.1109/ISVLSI.2016.13

R. Ragavan, C. Killian, O. Sentieys

{"title":"Adaptive Overclocking and Error Correction Based on Dynamic Speculation Window","authors":"R. Ragavan, C. Killian, O. Sentieys","doi":"10.1109/ISVLSI.2016.13","DOIUrl":"https://doi.org/10.1109/ISVLSI.2016.13","url":null,"abstract":"Error detection and correction based on double-sampling is used as common technique to handle timing errors while scaling Vdd for energy efficiency. An additional sampling element is inserted in the critical paths of the design, to double sample the outputs of those logic paths at different time instances that may fail while scaling the supply voltage or the clock frequency of the design. However, overclocking, and error detection and correction capabilities of the double sampling methods are limited due to the fixed speculation window which lacks adaptability for tracking variations such as temperature. In this paper, we introduce a dynamic speculation window to be used in double sampling schemes for timing error detection and correction in pipelined logic paths. The proposed method employs online slack measurement and conventional shadow flipflop approach to adaptively overclock or underclock the design and also to detect and correct timing errors due to temperature and other variability effects. We demonstrate this method in the Xilinx Virtex VC707 FPGA for various benchmarks. We achieve a maximum of 71% overclocking with a limited area overhead of 1.9% LUTs and 1.7% flip-flops.","PeriodicalId":140647,"journal":{"name":"2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)","volume":"60 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-07-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115510263","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 11

A Scalable Design Approach to Efficiently Map Applications on CGRAs 一种高效映射应用程序的可扩展设计方法

2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2016-07-11 DOI: 10.1109/ISVLSI.2016.54

Satyajit Das, T. Peyret, Kevin J. M. Martin, G. Corre, M. Thévenin, P. Coussy

引用次数: 11

Techniques for Improved Reliability in Memristive Crossbar PUF Circuits 提高记忆栅PUF电路可靠性的技术

2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2016-07-11 DOI: 10.1109/ISVLSI.2016.33

Mesbah Uddin, M. Majumder, G. Rose, K. Beckmann, H. Manem, Z. Alamgir, N. Cady

{"title":"Techniques for Improved Reliability in Memristive Crossbar PUF Circuits","authors":"Mesbah Uddin, M. Majumder, G. Rose, K. Beckmann, H. Manem, Z. Alamgir, N. Cady","doi":"10.1109/ISVLSI.2016.33","DOIUrl":"https://doi.org/10.1109/ISVLSI.2016.33","url":null,"abstract":"Hardware security has emerged as an important field of study aimed at mitigating issues such as integrated circuit (IC) piracy and counterfeiting. One popular solution for such hardware security attacks are physically unclonable functions (PUF) which provide a hardware specific unique identification based on intrinsic process variations within individual integrated circuit implementations. At the same time, as technology scaling progresses further into the nanometer region, emerging nanoelectronic technologies such as memristors become viable options. Several examples of nanoelectronic memristor-based PUF circuits have been proposed in the last few years. In this paper, we analyze the behavior of crossbar memristive PUF circuits under different environmental conditions such as varying temperature, supply rail voltage fluctuations and aging. We also present an approach that improves the reliability of these circuits, taking environmental variations into consideration. The advantages and challenges associated with these PUFs are also discussed in detail. Specifically, we show results for security metrics including reliability, uniqueness and uniformity. These security performance results are presented alongside estimates for power, area and delay showing the advantages of using nanoelectronic PUFs from the perspective of efficient resource utilization.","PeriodicalId":140647,"journal":{"name":"2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-07-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130092337","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 32

Cost and Thermal Analysis of High-Performance 2.5D and 3D Integrated Circuit Design Space 高性能2.5D和3D集成电路设计空间的成本和热分析

2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2016-07-11 DOI: 10.1109/ISVLSI.2016.133

Dylan C. Stow, Itir Akgun, Russell Barnes, P. Gu, Yuan Xie

{"title":"Cost and Thermal Analysis of High-Performance 2.5D and 3D Integrated Circuit Design Space","authors":"Dylan C. Stow, Itir Akgun, Russell Barnes, P. Gu, Yuan Xie","doi":"10.1109/ISVLSI.2016.133","DOIUrl":"https://doi.org/10.1109/ISVLSI.2016.133","url":null,"abstract":"3D Integration is a promising technology to continue the trend of Moore's law. However, higher density from die stacking introduces thermal challenges that require more expensive packaging and cooling solutions. An alternative integration technology is interposer-based 2.5D design, which has fewer thermal issues but adds extra interposer cost. Designers must be aware of the system-level cost benefits of these choices early in the design process. This paper presents a cost analysis model with wafer costs, 3D bonding costs, and thermal modeling for the optimization of package and cooling costs. The cost model is used to explore the design space of integrated circuits to determine cost-driven enabling points of 2.5D and 3D integration under consideration of design size and power density. Our results suggest that proper use of die-integration technologies can realize substantial cost savings over traditional 2D design, even with the inclusion of packaging and cooling costs. When thermal properties are considered, interposer-based 2.5D integration is predicted to be more cost effective than TSV-based 3D integration, especially when power density is high.","PeriodicalId":140647,"journal":{"name":"2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)","volume":"85 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-07-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123586087","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 11