2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)最新文献_第10页

Soft Error Effect Tolerant Temporal Self-Voting Checkers: Energy vs. Resilience Tradeoffs 软错误效应容忍时间自我投票检查:能量与弹性权衡

2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2016-07-01 DOI: 10.1109/ISVLSI.2016.19

Faris S. Alghareb, Mingjie Lin, R. Demara

{"title":"Soft Error Effect Tolerant Temporal Self-Voting Checkers: Energy vs. Resilience Tradeoffs","authors":"Faris S. Alghareb, Mingjie Lin, R. Demara","doi":"10.1109/ISVLSI.2016.19","DOIUrl":"https://doi.org/10.1109/ISVLSI.2016.19","url":null,"abstract":"Achieving high reliability against transient faults poses significant challenges due to the trends of technology and voltage scaling. Thus, numerous soft error mitigation techniques have been proposed for masking Soft Error Rate (SER) in logic circuits. However, most soft error suppression approaches have significant overheads in terms of area, power consumption, and speed performance degradation. Herein, we propose two circuit-level techniques, namely Temporal Self-Voting Logic (TSVL) and Hybrid Spatial and Temporal Redundancy Double-Error Correction (HSTR-DEC), to prevent the effects of soft errors in logic circuits, occurring due to Single Event Upset (SEU) or Single Event Transient (SET). TSVL and HSTR-DEC circuits can be utilized to improve the reliability of a logic path with minimal impact on circuit delay while achieving a complete and cost-effective SEU handling as compared to traditional spatial or temporal redundancy approach. The primary contribution of the TSVL approach is that it eliminates error masking from the critical datapath, thus, area and energy overheads are significantly reduced. A transient gate-level fault injection and analysis is used to evaluate the capability of soft errors suppression of the proposed hardening approach. Experimental results indicate that TSVL can cover soft errors, on average, roughly by 99% while realizing an amelioration of 22.02% and 2.15% for area and speed degradation as compared to the previous Self-Voting DMR approach. Meanwhile, HSTRDEC approach realizes a complete coverage for single and double SEUs while incurring comparable area and delay overheads as compared to the prior hybrid redundancy approach.","PeriodicalId":140647,"journal":{"name":"2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116939371","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4

A Designer's Rationale for Nanoelectronic Hardware Security Primitives 纳米电子硬件安全原语的设计原理

2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2016-07-01 DOI: 10.1109/ISVLSI.2016.114

G. Rose, Mesbah Uddin, M. Majumder

{"title":"A Designer's Rationale for Nanoelectronic Hardware Security Primitives","authors":"G. Rose, Mesbah Uddin, M. Majumder","doi":"10.1109/ISVLSI.2016.114","DOIUrl":"https://doi.org/10.1109/ISVLSI.2016.114","url":null,"abstract":"A variety of hardware security primitives have been developed in recent years, aimed at mitigating issues such as integrated circuit (IC) piracy, counterfeiting, and side-channel analysis. For example, a popular security primitive for mitigating such hardware security vulnerabilities is the physical unclonable function (PUF) which provides hardware specific unique identification based on intrinsic process variations in individual integrated circuit implementations. At the same time, as technology scaling progresses further into the nanometer region, emerging nanoelectronic technologies are becoming viable options for many next-generation computing technologies. At the intersection between nanoelectronics and security, several examples of nano-enabled security primitives have been proposed in the last few years. In this paper, we consider a few examples of nanoelectronic security in the context of how such nanoscale technologies impact power, area and delay as compared to conventional CMOS-based approaches. Our analyses show that leveraging novel nanoelectronic technologies not only provide area benefits but also energy-efficient solutions that enable security with a small footprint.","PeriodicalId":140647,"journal":{"name":"2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121839905","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 7

Joint Soft-Error-Rate (SER) Estimation for Combinational Logic and Sequential Elements 组合逻辑和顺序元素的联合软错误率估计

2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2016-07-01 DOI: 10.1109/ISVLSI.2016.28

Ji Li, J. Draper

{"title":"Joint Soft-Error-Rate (SER) Estimation for Combinational Logic and Sequential Elements","authors":"Ji Li, J. Draper","doi":"10.1109/ISVLSI.2016.28","DOIUrl":"https://doi.org/10.1109/ISVLSI.2016.28","url":null,"abstract":"With drastic device shrinking, low operating voltages, increasing complexities, and high speed operations, radiation-induced soft errors have posed an ever increasing reliability challenge to both combinational and sequential circuits in advanced CMOS technologies. Therefore, it is imperative to devise efficient soft error rate (SER) estimation methods, in order to evaluate the soft error vulnerabilities for cost-effective robust circuit design. Previous works either analyze only SER in combinational circuits or evaluate soft error vulnerabilities in sequential elements. In this paper, a joint SER estimation framework is proposed, which considers single-event transients (SETs) in combinational logic and multiple cell upsets (MCUs) in sequential components. Various masking effects are considered in the combinational SER estimation process, and several typical radiation-hardened and non-hardened flip-flop structures are analyzed and compared as the sequential elements. A schematic and layout co-simulation approach is proposed to model the MCUs for redundant sequential storage structures. Experimental results of a variety of ISCAS benchmark circuits using the Nangate 45nm CMOS standard cell library demonstrate the difference in soft error resilience among designs using different sequential elements and the importance of modeling MCUs in redundant structures.","PeriodicalId":140647,"journal":{"name":"2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133942602","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 13

Gate Overdrive with Split-Circuit Biasing to Substitute for Body Biasing in FinFET and UTB FDSOI Circuits 用分路偏置取代FinFET和UTB FDSOI电路中的体偏置的门超速驱动

2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2016-07-01 DOI: 10.1109/ISVLSI.2016.136

Andrew Whetzel, M. Stan

{"title":"Gate Overdrive with Split-Circuit Biasing to Substitute for Body Biasing in FinFET and UTB FDSOI Circuits","authors":"Andrew Whetzel, M. Stan","doi":"10.1109/ISVLSI.2016.136","DOIUrl":"https://doi.org/10.1109/ISVLSI.2016.136","url":null,"abstract":"Body biasing (BB) in bulk CMOS is an important tool for circuit designers that enables dynamic modulation of device thresholds post-fabrication, thus potentially improving yields, or allowing the circuit to adapt to different power modes, such as fully active or sleep. Fully-depleted silicon-on-insulator (FDSOI) FETs, such as ultrathin body (UTB) devices, may benefit from the same effect when the buried oxide (BOX) is thin enough to allow back plane biasing (BPB) to affect the accumulation or inversion in the channel. However, when the BOX is thick the back plane potential has very little effect on the channel, eliminating the ability to modulate threshold voltage via BPB. Similarly, FinFETs benefit very little from controlled body effect because the gate has nearly full control over the channel. In this paper a new circuit topology is presented which can act as a substitute for body biasing without relying on the body effect. The inputs, outputs, and supply rails are split in such a way that the gates of some devices are overdriven without increasing voltage swing, resulting in a higher Ion and reduced latency under forward bias, or reducing leakage current under reverse bias. For a 28nm FDSOI process a speedup of up to 15% can be realized under forward bias with an increase in power of 19%, while static power can be reduced by up to 35% with a 19% decrease in performance.","PeriodicalId":140647,"journal":{"name":"2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134006563","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Design and Analysis of Novel InSb/Si Heterojunction Double Gate Tunnel Field Effect Transistor 新型InSb/Si异质结双栅隧道场效应晶体管的设计与分析

2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2016-07-01 DOI: 10.1109/ISVLSI.2016.52

S. Ahish, D. Sharma, M. H. Vasantha, Kumar Y. B. Nithin

引用次数: 7

STA: A Highly Scalable Low Latency Butterfly Fat Tree Based 3D NoC Design STA:一个高度可扩展的低延迟蝴蝶脂肪树的3D NoC设计

2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2016-07-01 DOI: 10.1109/ISVLSI.2016.127

Avik Bose, P. Ghosal, S. Mohanty

{"title":"STA: A Highly Scalable Low Latency Butterfly Fat Tree Based 3D NoC Design","authors":"Avik Bose, P. Ghosal, S. Mohanty","doi":"10.1109/ISVLSI.2016.127","DOIUrl":"https://doi.org/10.1109/ISVLSI.2016.127","url":null,"abstract":"Since the past decade Network-on-Chip has evolved as the most dominant and efficient solution in on-chip communication paradigm for multi-core systems. With the growing number of on-chip processing cores modern three dimensional NoC design is facing several challenges originating from various network performance parameters like latency, hop count etc. Scalability and network efficiency have generated an important trade off in 3D NoC design, which needs to be balanced, especially for application specific NoC design. Tree based topologies outperform mesh based topologies in terms of network latency and throughput with increasing injection rate of packets/flits. But on the other hand, floor planing becomes much more complex for tree based designs with increasing number of IP blocks compared to mesh due to the hierarchical structure. This paper introduces a novel 3D NoC architecture named Split Tree Architecture (STA), based on butterfly fat tree, which is highly scalable while maintaining low network latency and hop count significantly. There are latency improvements of 51-91%, 84-96%, 55-96%, and 48-96% over mesh, torus, butterfly, and flattened butterfly topologies respectively. Average hop count is improved by 44% and 30% over mesh and torus. Average and minimum acceptance rates are improved by 3-8% and 3-12% over torus and, 4-7% and 4-12% over flattened butterfly. In comparison to the previously reported state of the art 3D BFT based designs, STA achieves performance improvements of 19-78%, 2-42%, 0.2-0.6%, and around 20%, for average latency, average acceptance rate, minimum acceptance rate, and average hop count respectively.","PeriodicalId":140647,"journal":{"name":"2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130927001","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

SecCheck: A Trustworthy System with Untrusted Components SecCheck:一个具有不可信组件的可信系统

2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2016-07-01 DOI: 10.1109/ISVLSI.2016.31

Rajshekar Kalayappan, S. Sarangi

引用次数: 4

LLPA: Logic State Based Leakage Power Analysis 基于逻辑状态的泄漏功率分析

2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2016-07-01 DOI: 10.1109/ISVLSI.2016.121

S. Dhanuskodi, S. Keshavarz, Daniel E. Holcomb

引用次数: 2

Design of Division Circuits for Stochastic Computing 随机计算的除法电路设计

2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2016-07-01 DOI: 10.1109/ISVLSI.2016.48

Te-Hsuan Chen, J. Hayes

引用次数: 37

Hardware/Software Isolation and Protection Architecture for Transparent Security Enforcement in Networked Devices 用于网络设备透明安全执行的硬件/软件隔离和保护体系结构

2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2016-07-01 DOI: 10.1109/ISVLSI.2016.32

Festus Hategekimana, Pierre-Alexis Nardin, C. Bobda

{"title":"Hardware/Software Isolation and Protection Architecture for Transparent Security Enforcement in Networked Devices","authors":"Festus Hategekimana, Pierre-Alexis Nardin, C. Bobda","doi":"10.1109/ISVLSI.2016.32","DOIUrl":"https://doi.org/10.1109/ISVLSI.2016.32","url":null,"abstract":"We present an integrated hardware/software architectureto enforce security in networked workstations andembedded devices such as printers and microscopes. Thesedevices are usually connected to the Internet without protection, so they are exposed to attack. Our solution operatesas an intermediate isolation and protection module (IPM) between the network and the device to be protected. TheIPM can be implemented as a dedicated IP on a system-onchip, or as a separate chip to analyze incoming and outgoingtraffic for malicious activities, in a transparent way to thedevice under protection. Security enforcement is performedin two stages. A deep packet inspection module is used inthe first stage to detect and drop packets originating fromknown blacklisted domains or carrying malware patterns, simultaneously important features from protocol-conformingpackets are extracted and sent to a binary classifier for furtherprocessing and decision making. The second stage uses a binaryclassifier to make decisions on seemingly protocol-conformingpackets. We designed and implemented a prototype of theIPM as a system-on-FPGA, with packet filtering and analysisaccelerated in hardware, and binary classification and decisionmaking in software. The IPM operates at high-speed witha very small footprint, suitable for embedded devices withfewer resources. Evaluation of our prototype using the 1999Knowledge Discovery in Databases (KDD Cup 1999 dataset) benchmarks shows a high detection rate on various distributeddenial-of-service (DDoS) attacks such as Neptune DoS (99.3%),Smurf DoS (100%), and Teardrop DoS (98.90%).","PeriodicalId":140647,"journal":{"name":"2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128980573","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 7