S. Ahish, D. Sharma, M. H. Vasantha, Kumar Y. B. Nithin
{"title":"Design and Analysis of Novel InSb/Si Heterojunction Double Gate Tunnel Field Effect Transistor","authors":"S. Ahish, D. Sharma, M. H. Vasantha, Kumar Y. B. Nithin","doi":"10.1109/ISVLSI.2016.52","DOIUrl":null,"url":null,"abstract":"In this work, an InSb/Si heterojunction hetero gate dielectric double gate TFET (HTFET) having a split pocket at Source-Channel junction has been designed and its analog/RF performance has been investigated. The analog/RF performance of the device is analysed in terms of I-V characteristics, transconsuctance (gm), parasitic capacitances, cut-off frequency (fT) and gain bandwidth product (GBW). Maximum fT of 777.8 GHz, maximum GBW of 393 GHz and a ION/IOFF ratio of 1010 were obtained from the simulations carried out. Further, circuit level performance analysis is performed by implementing a common source (CS) amplifier based on HTFET, using look-up table based Verilog-A model; a 3-dB roll-off frequency of 55.0981 GHz and unity gain cut-off frequency of 1.4652 THz were achieved.","PeriodicalId":140647,"journal":{"name":"2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2016-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"7","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISVLSI.2016.52","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 7
Abstract
In this work, an InSb/Si heterojunction hetero gate dielectric double gate TFET (HTFET) having a split pocket at Source-Channel junction has been designed and its analog/RF performance has been investigated. The analog/RF performance of the device is analysed in terms of I-V characteristics, transconsuctance (gm), parasitic capacitances, cut-off frequency (fT) and gain bandwidth product (GBW). Maximum fT of 777.8 GHz, maximum GBW of 393 GHz and a ION/IOFF ratio of 1010 were obtained from the simulations carried out. Further, circuit level performance analysis is performed by implementing a common source (CS) amplifier based on HTFET, using look-up table based Verilog-A model; a 3-dB roll-off frequency of 55.0981 GHz and unity gain cut-off frequency of 1.4652 THz were achieved.