Low Cost VLSI Architecture for Sample Adaptive Offset Encoder in HEVC

Sample Adaptive Offset (SAO) has been adopted as a new in-loop filtering block in High Efficiency Video Coding (HEVC). It can significantly increase compression efficiency especially for sequences that contain computer graphics content up to 23%. To get the optimum SAO parameters, exhaustive operations are required because of the huge amount of samples which the encoder has to study. In this work, a low cost high throughput VLSI implementation for the parameter estimation (encoding) phase is proposed. The proposed novel architecture reduces the cost in terms of gates count by 47% in comparison with prior work. The proposed design is prototyped using 65 nm CMOS technology. It has 89.3 Kgates, 8832 bits SRAM, and a maximum clock frequency of 426 MHz. It can support real time 8K×4K@120fps videos at 378 MHz.