2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)最新文献_第9页

Accurate Synthesis of Arithmetic Operations with Stochastic Logic 算术运算与随机逻辑的精确综合

2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2016-07-01 DOI: 10.1109/ISVLSI.2016.74

E. Vahapoglu, M. Altun

引用次数: 11

A Low-Cost Mixed Clock Generator for High Speed Adiabatic Logic 用于高速绝热逻辑的低成本混合时钟发生器

2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2016-07-01 DOI: 10.1109/ISVLSI.2016.44

Zhou Zhao, A. Srivastava, Lu Peng, S. Mohanty

引用次数: 2

A System-Level Exploration of Power Delivery Architectures for Near-Threshold Manycores Considering Performance Constraints 考虑性能约束的近阈值多核供电架构的系统级探索

2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2016-07-01 DOI: 10.1109/ISVLSI.2016.65

Ioannis S. Stamelakos, A. Djahromi, A. Eltawil, G. Palermo, C. Silvano, F. Kurdahi

引用次数: 2

Low-Power and High Performance Sinusoidal Clocked Dynamic Circuit Design 低功耗高性能正弦时钟动态电路设计

2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2016-07-01 DOI: 10.1109/ISVLSI.2016.34

Raghava Katreepalli, Hemanth Chemanchula, T. Haniotakis, Y. Tsiatouhas

引用次数: 1

Using Statistical Models to Improve the Reliability of Delay-Based PUFs 利用统计模型提高时延puf的可靠性

2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2016-07-01 DOI: 10.1109/ISVLSI.2016.125

Xiaolin Xu, W. Burleson, Daniel E. Holcomb

引用次数: 31

A Pruning Technique for B&B Based Design Exploration of Approximate Computing Variants 基于B&B的近似计算变量设计探索的剪枝技术

2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2016-07-01 DOI: 10.1109/ISVLSI.2016.110

M. Barbareschi, F. Iannucci, A. Mazzeo

引用次数: 10

Thermal-Aware Preemptive Test Scheduling for Network-on-Chip Based 3D ICs 基于片上网络的3D集成电路热感知抢占式测试调度

2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2016-07-01 DOI: 10.1109/ISVLSI.2016.75

K. Manna, C. S. Sagar, S. Chattopadhyay, I. Sengupta

引用次数: 1

A Designer's Rationale for Nanoelectronic Hardware Security Primitives 纳米电子硬件安全原语的设计原理

2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2016-07-01 DOI: 10.1109/ISVLSI.2016.114

G. Rose, Mesbah Uddin, M. Majumder

{"title":"A Designer's Rationale for Nanoelectronic Hardware Security Primitives","authors":"G. Rose, Mesbah Uddin, M. Majumder","doi":"10.1109/ISVLSI.2016.114","DOIUrl":"https://doi.org/10.1109/ISVLSI.2016.114","url":null,"abstract":"A variety of hardware security primitives have been developed in recent years, aimed at mitigating issues such as integrated circuit (IC) piracy, counterfeiting, and side-channel analysis. For example, a popular security primitive for mitigating such hardware security vulnerabilities is the physical unclonable function (PUF) which provides hardware specific unique identification based on intrinsic process variations in individual integrated circuit implementations. At the same time, as technology scaling progresses further into the nanometer region, emerging nanoelectronic technologies are becoming viable options for many next-generation computing technologies. At the intersection between nanoelectronics and security, several examples of nano-enabled security primitives have been proposed in the last few years. In this paper, we consider a few examples of nanoelectronic security in the context of how such nanoscale technologies impact power, area and delay as compared to conventional CMOS-based approaches. Our analyses show that leveraging novel nanoelectronic technologies not only provide area benefits but also energy-efficient solutions that enable security with a small footprint.","PeriodicalId":140647,"journal":{"name":"2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121839905","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 7

Soft Error Effect Tolerant Temporal Self-Voting Checkers: Energy vs. Resilience Tradeoffs 软错误效应容忍时间自我投票检查:能量与弹性权衡

2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2016-07-01 DOI: 10.1109/ISVLSI.2016.19

Faris S. Alghareb, Mingjie Lin, R. Demara

{"title":"Soft Error Effect Tolerant Temporal Self-Voting Checkers: Energy vs. Resilience Tradeoffs","authors":"Faris S. Alghareb, Mingjie Lin, R. Demara","doi":"10.1109/ISVLSI.2016.19","DOIUrl":"https://doi.org/10.1109/ISVLSI.2016.19","url":null,"abstract":"Achieving high reliability against transient faults poses significant challenges due to the trends of technology and voltage scaling. Thus, numerous soft error mitigation techniques have been proposed for masking Soft Error Rate (SER) in logic circuits. However, most soft error suppression approaches have significant overheads in terms of area, power consumption, and speed performance degradation. Herein, we propose two circuit-level techniques, namely Temporal Self-Voting Logic (TSVL) and Hybrid Spatial and Temporal Redundancy Double-Error Correction (HSTR-DEC), to prevent the effects of soft errors in logic circuits, occurring due to Single Event Upset (SEU) or Single Event Transient (SET). TSVL and HSTR-DEC circuits can be utilized to improve the reliability of a logic path with minimal impact on circuit delay while achieving a complete and cost-effective SEU handling as compared to traditional spatial or temporal redundancy approach. The primary contribution of the TSVL approach is that it eliminates error masking from the critical datapath, thus, area and energy overheads are significantly reduced. A transient gate-level fault injection and analysis is used to evaluate the capability of soft errors suppression of the proposed hardening approach. Experimental results indicate that TSVL can cover soft errors, on average, roughly by 99% while realizing an amelioration of 22.02% and 2.15% for area and speed degradation as compared to the previous Self-Voting DMR approach. Meanwhile, HSTRDEC approach realizes a complete coverage for single and double SEUs while incurring comparable area and delay overheads as compared to the prior hybrid redundancy approach.","PeriodicalId":140647,"journal":{"name":"2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116939371","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4

Power-Delay-Area Performance Modeling and Analysis for Nano-Crossbar Arrays 纳米交叉棒阵列的功率延迟区性能建模与分析

2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2016-07-01 DOI: 10.1109/ISVLSI.2016.100

Muhammed Ceylan Morgül, Furkan Peker, M. Altun

{"title":"Power-Delay-Area Performance Modeling and Analysis for Nano-Crossbar Arrays","authors":"Muhammed Ceylan Morgül, Furkan Peker, M. Altun","doi":"10.1109/ISVLSI.2016.100","DOIUrl":"https://doi.org/10.1109/ISVLSI.2016.100","url":null,"abstract":"In this study, we introduce an accurate capacitor-resistor model for nano-crossbar arrays that is to be used for power/delay/area performance analysis and optimization. Although the proposed model is technology independent, we explicitly show its applicability for three different nanoarray technologies where each crosspoint behaves as a diode, a FET, and a four-terminal switch. In order to find related capacitor and resistor values, we investigate upper/lower value limits for technology dependent parameters including doping concentration, nanowire dimension, pitch size, and layer thickness. We also use different fan-out capacitors to test the integration capability of these technologies. Comparison between the proposed model and a conventional simple one, which generally uses one/two capacitors for each crosspoint, demonstrates the necessity of using our model in order to accurately calculate power and delay values. The only exception where both models give approximately same results is the presence of considerably low valued resistive connections between switches. However, we show that this is a rare case for nano-crossbar technologies.","PeriodicalId":140647,"journal":{"name":"2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124090614","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 5