2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)最新文献_第9页

Accurate Synthesis of Arithmetic Operations with Stochastic Logic 算术运算与随机逻辑的精确综合

2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2016-07-01 DOI: 10.1109/ISVLSI.2016.74

E. Vahapoglu, M. Altun

引用次数: 11

A Low-Cost Mixed Clock Generator for High Speed Adiabatic Logic 用于高速绝热逻辑的低成本混合时钟发生器

2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2016-07-01 DOI: 10.1109/ISVLSI.2016.44

Zhou Zhao, A. Srivastava, Lu Peng, S. Mohanty

引用次数: 2

A System-Level Exploration of Power Delivery Architectures for Near-Threshold Manycores Considering Performance Constraints 考虑性能约束的近阈值多核供电架构的系统级探索

2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2016-07-01 DOI: 10.1109/ISVLSI.2016.65

Ioannis S. Stamelakos, A. Djahromi, A. Eltawil, G. Palermo, C. Silvano, F. Kurdahi

引用次数: 2

Low-Power and High Performance Sinusoidal Clocked Dynamic Circuit Design 低功耗高性能正弦时钟动态电路设计

2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2016-07-01 DOI: 10.1109/ISVLSI.2016.34

Raghava Katreepalli, Hemanth Chemanchula, T. Haniotakis, Y. Tsiatouhas

引用次数: 1

Using Statistical Models to Improve the Reliability of Delay-Based PUFs 利用统计模型提高时延puf的可靠性

2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2016-07-01 DOI: 10.1109/ISVLSI.2016.125

Xiaolin Xu, W. Burleson, Daniel E. Holcomb

引用次数: 31

A Pruning Technique for B&B Based Design Exploration of Approximate Computing Variants 基于B&B的近似计算变量设计探索的剪枝技术

2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2016-07-01 DOI: 10.1109/ISVLSI.2016.110

M. Barbareschi, F. Iannucci, A. Mazzeo

引用次数: 10

Power-Delay-Area Performance Modeling and Analysis for Nano-Crossbar Arrays 纳米交叉棒阵列的功率延迟区性能建模与分析

2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2016-07-01 DOI: 10.1109/ISVLSI.2016.100

Muhammed Ceylan Morgül, Furkan Peker, M. Altun

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引用次数: 5

Low Cost VLSI Architecture for Sample Adaptive Offset Encoder in HEVC HEVC中样本自适应偏移编码器的低成本VLSI架构

2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2016-07-01 DOI: 10.1109/ISVLSI.2016.78

Sayed El Gendy, A. Shalaby, M. Sayed

引用次数: 2

Thermal-Aware Preemptive Test Scheduling for Network-on-Chip Based 3D ICs 基于片上网络的3D集成电路热感知抢占式测试调度

2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2016-07-01 DOI: 10.1109/ISVLSI.2016.75

K. Manna, C. S. Sagar, S. Chattopadhyay, I. Sengupta

引用次数: 1

Architecture Exploration for Energy-Efficient Embedded Vision Applications: From General Purpose Processor to Domain Specific Accelerator 节能嵌入式视觉应用的架构探索:从通用处理器到特定领域加速器

2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2016-07-01 DOI: 10.1109/ISVLSI.2016.112

Maria Malik, Farnoud Farahmand, P. Otto, N. Akhlaghi, T. Mohsenin, S. Sikdar, H. Homayoun

{"title":"Architecture Exploration for Energy-Efficient Embedded Vision Applications: From General Purpose Processor to Domain Specific Accelerator","authors":"Maria Malik, Farnoud Farahmand, P. Otto, N. Akhlaghi, T. Mohsenin, S. Sikdar, H. Homayoun","doi":"10.1109/ISVLSI.2016.112","DOIUrl":"https://doi.org/10.1109/ISVLSI.2016.112","url":null,"abstract":"OpenCV applications are computationally intensive tasks among computer vision algorithms. The demand for low power yet high performance real-time processing of OpenCV embedded vision applications have led to developing their customized implementations on state-of-the-art embedded processing platforms. Given the industry move to heterogeneous platforms which integrates single core or multicore CPU with on-chip FPGA accelerators and GPU accelerators, the question of what platform and what implementation, whether hardware or software, is best suited for energy-efficient processing of this class of applications is becoming important. In this paper, we seek to answer this question through a detailed hardware and software implementation of OpenCV applications and methodically measurement and comprehensive analysis of their power and performance on state-of-the-art heterogeneous embedded processing platforms. The results show that in addition to application behavior, the size of image is an important factor in deciding the efficient platform in terms of highest energy-efficiency (EDP) among hardware accelerators on FPGA and software accelerators on GPU and multicore CPUs. While hardware implementation on ZYNQ shown to be the most performance and energy-efficient for image size of 500x500 or less, software GPU implementation found to be the most efficient and achieves highest speedup for larger image sizes. In addition, while for compute intensive vision applications the gap between FPGA, CPU and GPU reduces as the size of image increases, for non-intensive applications, a large performance and EDP gap is observed between the studied platforms, as the size of the image increases.","PeriodicalId":140647,"journal":{"name":"2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123090613","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 14