2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)最新文献_第4页

Design and Characterization of the TERO-PUF on SRAM FPGAs SRAM fpga上TERO-PUF的设计与表征

2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2016-07-11 DOI: 10.1109/ISVLSI.2016.18

Cédric Marchand, L. Bossuet, A. Cherkaoui

引用次数: 5

An Accurate All CMOS Bandgap Reference Voltage with Integrated Temperature Sensor for IoT Applications 一个精确的全CMOS带隙参考电压集成温度传感器的物联网应用

2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2016-07-11 DOI: 10.1109/ISVLSI.2016.115

Sunil Kumar Maddikatla, S. Jandhyala

{"title":"An Accurate All CMOS Bandgap Reference Voltage with Integrated Temperature Sensor for IoT Applications","authors":"Sunil Kumar Maddikatla, S. Jandhyala","doi":"10.1109/ISVLSI.2016.115","DOIUrl":"https://doi.org/10.1109/ISVLSI.2016.115","url":null,"abstract":"An accurate, robust CMOS voltage reference biased in subthreshold region with integrated temperature sensor circuit has been proposed in 180nm technology node using UMC RF process for IoT and low cost SoC applications. In UMC 180nm node the proposed reference voltage has an accuracy of 65 ppm/°C over 3σ variation in process and ±10% variation in supply, in the temperature range -40°C to 100°C. The proposed design achieves an accurate reference voltage and proportional to absolute temperature (PTAT) voltage at reduced process corner dependence, using a process invariant circuit in conjunction with a supply independent biasing circuit. The supply sensitivity of the output voltage is 4000 ppm/V at UMC 180nm. The proposed reference voltage in UMC 180nm technology consumes 12μW of power and is used for low power applications. The output voltage is 266mV at room temperature (27°C) in typical corner. The proposed reference voltage has been adjusted for process variation in MOSFETs and Resistors using a resistor trimming circuit. Noise analysis and supply sensitivity have been analyzed to prove the robustness of the proposed reference voltage design.","PeriodicalId":140647,"journal":{"name":"2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)","volume":"397-400 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-07-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131229592","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

System Design for In-Hardware STDP Learning and Spiking Based Probablistic Inference 基于概率推理的硬件内STDP学习和峰值系统设计

2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2016-07-11 DOI: 10.1109/ISVLSI.2016.91

Khadeer Ahmed, Amar Shrestha, Yanzhi Wang, Qinru Qiu

{"title":"System Design for In-Hardware STDP Learning and Spiking Based Probablistic Inference","authors":"Khadeer Ahmed, Amar Shrestha, Yanzhi Wang, Qinru Qiu","doi":"10.1109/ISVLSI.2016.91","DOIUrl":"https://doi.org/10.1109/ISVLSI.2016.91","url":null,"abstract":"The emerging field of neuromorphic computing is offering a possible pathway for approaching the brain's computing performance and energy efficiency for cognitive applications such as pattern recognition, speech understanding, natural language processing etc. In spiking neural networks (SNNs), information is encoded as sparsely distributed spike trains, enabling learning through the spike-timing dependent plasticity (STDP) mechanism. SNNs can potentially achieve ultra-low power consumption and distributed learning due to the inherent asynchronous and sparse inter-neuron communications. Several inroads have been made in SNN implementations, however, there is still a lack of computational models that lead to hardware implementation of large scale SNN with STDP capabilities. In this work, we present a set of neuron models and neuron circuit motifs that form SNNs capable of in-hardware fully-distributed STDP learning and spiking based probabilistic inference. Functions such as efficient Bayesian inference and unsupervised Hebbian learning are demonstrated on the proposed SNN system design. A highly scalable and flexible digital hardware implementation of the neuron model is also presented. Experimental results on two different applications: unsupervised feature extraction and inference based sentence construction, have demonstrated the proposed design's effectiveness in learning and inference.","PeriodicalId":140647,"journal":{"name":"2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-07-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133034189","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 6

Impact of VT and Body-Biasing on Resistive Short Detection in 28nm UTBB FDSOI -- LVT and RVT Configurations VT和体偏置对28nm UTBB FDSOI - LVT和RVT阻性短探测的影响

2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2016-07-11 DOI: 10.1109/ISVLSI.2016.102

Amit Karel, M. Comte, J. Gallière, F. Azaïs, M. Renovell

引用次数: 11

Design of Low-Power High-Gain Operational Amplifier for Bio-Medical Applications 生物医学用低功率高增益运算放大器的设计

2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2016-07-11 DOI: 10.1109/ISVLSI.2016.62

S. S. Rajput, Ashish Singh, A. Chandel, R. Chandel

引用次数: 8

Device Circuit Co Design of FEFET Based Logic for Low Voltage Processors 基于FEFET逻辑的低压处理器器件电路设计

2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2016-07-11 DOI: 10.1109/ISVLSI.2016.116

Sumitha George, Ahmedullah Aziz, Xueqing Li, M. Kim, S. Datta, J. Sampson, S. Gupta, N. Vijaykrishnan

引用次数: 43

Selective Enhancement of Randomness at the Materials Level: Poly-Si Based Physical Unclonable Functions (PUFs) 材料水平随机性的选择性增强:基于多晶硅的物理不可克隆函数(puf)

2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2016-07-11 DOI: 10.1109/ISVLSI.2016.55

Haoting Shen, Fahim Rahman, Bicky Shakya, M. Tehranipoor, Domenic Forte

{"title":"Selective Enhancement of Randomness at the Materials Level: Poly-Si Based Physical Unclonable Functions (PUFs)","authors":"Haoting Shen, Fahim Rahman, Bicky Shakya, M. Tehranipoor, Domenic Forte","doi":"10.1109/ISVLSI.2016.55","DOIUrl":"https://doi.org/10.1109/ISVLSI.2016.55","url":null,"abstract":"Physically Unclonable Functions (PUFs) were introduced over a decade ago for a variety of security applications. Silicon PUFs exploit uncontrollable random variations from manufacturing to generate unique and random signatures/responses. Existing research on PUFs has focused on either PUF design at the architectural level or optimization of lithography to increase sensitivity to random process variations. However, such sources of randomness may become limited during standard CMOS manufacturing as processes continue to mature especially with the advances in design for manufacturability. In this paper, poly-Si is proposed to improve PUF quality at the materials level. Compared to conventional single crystal Si (sc-Si), defects and trapped charges resulting from the random distribution of crystal grains and grain boundaries (GBs) in poly-Si offer considerable random variations. By using poly-Si only in the PUF region in devices, the randomness of the PUF can be enhanced without impacting other functional circuits and thus the IC yield can be maintained. RO-PUF simulation results based on a poly-Si field effect transistor (FET) model show that compared to sc-Si based PUFs, the reliability of poly-Si based PUFS can be improved from 89.18% to 98.82%.","PeriodicalId":140647,"journal":{"name":"2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-07-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131339084","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Design of Low Power 5-Bit Hybrid Flash ADC 低功耗5位混合闪存ADC的设计

2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2016-07-11 DOI: 10.1109/ISVLSI.2016.53

Mayur S M, S. R. K., Nithin Y. B. Kumar, Vasantha M

引用次数: 14

An Automated Hardware/Software Co-Design Flow for Partially Reconfigurable FPGAs 部分可重构fpga的自动化软硬件协同设计流程

2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2016-07-11 DOI: 10.1109/ISVLSI.2016.73

S. Yousuf, A. Gordon-Ross

引用次数: 10

A Low-Leakage, Robust ESD Clamp with Thyristor Delay Element in 65 nm CMOS Technology 65纳米CMOS技术中具有晶闸管延迟元件的低漏、稳健ESD箝位

2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2016-07-11 DOI: 10.1109/ISVLSI.2016.57

M. Elghazali, M. Sachdev, A. Opal

引用次数: 3