{"title":"Mixed-Signal Design Using Digital CAD","authors":"Vishnu Unnikrishnan, M. Vesterbacka","doi":"10.1109/ISVLSI.2016.79","DOIUrl":"https://doi.org/10.1109/ISVLSI.2016.79","url":null,"abstract":"The paper investigates the use of the existing CAD framework for digital circuit synthesis to design and synthesize a select set of mixed-signal functions like analog-to-digital and digital-to-analog conversions. This approach leads to fast and low cost design of technology portable system-on-chip solutions with analog interfaces. Some circuit examples for implementation of data conversion using digital circuits are discussed, leveraging on time-domain signal processing. Some of the signal corruption mechanisms in time-domain signal processing systems are considered in order to suggest adaptations to the existing digital design flow for the synthesis of mixed-signal circuits. As an example to show that high performance data conversion circuits can be realized using low accuracy general purpose components, an ADC is designed and synthesized with the vendor supplied standard cell library in a 65 nm CMOS process. Spectre simulation results show the feasibility of employing a digital CAD framework to synthesize high performance mixed-signal circuits, by applying time-domain signal processing.","PeriodicalId":140647,"journal":{"name":"2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-07-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121698657","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"An Improved Approach for the Synthesis of Boolean Functions Using Memristor Based IMPLY and INVERSE-IMPLY Gates","authors":"F. Lalchhandama, B. Sapui, K. Datta","doi":"10.1109/ISVLSI.2016.61","DOIUrl":"https://doi.org/10.1109/ISVLSI.2016.61","url":null,"abstract":"Research on memristors have drawn wide attention in recent years as these devices exhibit unique properties which can be used to perform various logic and memory operations. Memristor based memory systems are expected to replace flash memory devices in the near future. In addition, synthesis and optimization of boolean functions using memristors are becoming an important area of research. There are various logic design styles for memristors that have been reported, among which the one that implements material implication operation forms the basis of the present work. An IMPLY gate implements the implication operation, and can be realized using only two memristors and one resistance. In the present work, the widely available synthesis tool ABC is used for synthesizing an arbitrary boolean function into a netlist of IMPLY gates. To optimize the number of memristors to be used for the realization, we propose an INVERSE-IMPLY gate for handling fanouts in the intermediate netlist generated by the ABC tool. Synthesis experiments have been carried out on standard benchmark functions of up to 16 variables, which show an overall improvement of 22.8% in the number of steps required for evaluation over an existing stateof-the-art method. For functions with 9 or more variables, the improvement increases to 35.5%.","PeriodicalId":140647,"journal":{"name":"2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126865821","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Gayathri Ananthanarayanan, S. Sarangi, M. Balakrishnan
{"title":"Leakage Power Aware Task Assignment Algorithms for Multicore Platforms","authors":"Gayathri Ananthanarayanan, S. Sarangi, M. Balakrishnan","doi":"10.1109/ISVLSI.2016.43","DOIUrl":"https://doi.org/10.1109/ISVLSI.2016.43","url":null,"abstract":"Increased power density and high temperatures are looming issues in many-core processors. Technology scaling trends, cooling limitations, and stringent application requirements make these issues rather difficult to handle. Consequently, it is imperative to design solutions that are effective and also scale well with increasing core counts. In this work, we present an application mapping framework LeakOpt, which aims to minimize the total power consumption of manycore processors. We first demonstrate the implications of lateral heat conduction on leakage power consumption and show that heat spread aware task assignment can significantly impact the total power consumption. We formulate the mapping problem as an optimization problem and design a family of algorithms to solve it heuristically. We present simulation results that shows reduction upto 27.12% in leakage power consumption relative to worst case task mapping for a variety of workloads. Heuristic based mapping schemes perform 2600x faster (for 225 cores) while still within 2.5% of best case results. We further evaluate the same algorithms on a real hardware (TILE-Gx36TM) and show that these techniques can reduce leakage by upto 18.22% on average. Results on hardware are consistent with the simulation results as far as the relative effectiveness of various heuristics is concerned.","PeriodicalId":140647,"journal":{"name":"2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122104874","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Hardware Security Challenges Beyond CMOS: Attacks and Remedies","authors":"Kaveh Shamsi, Wujie Wen, Yier Jin","doi":"10.1109/ISVLSI.2016.93","DOIUrl":"https://doi.org/10.1109/ISVLSI.2016.93","url":null,"abstract":"The globalization of Integrated Circuits (ICs) supply chain has raised security concerns on how to ensure the integrity and the trustworthiness of fabricated circuits. While existing attack and protection methods are developed for CMOS based circuits, the introduction of emerging transistors acts as a double-sided sword. The usage of emerging devices introduces new security issues which the attackers can leverage to launch hardware attacks. On the other hand, the unique properties of emerging devices also provides a great opportunity for defenders to develop innovative hardware security primitives and to construct resilient hardware platforms for cybersecurity. In this paper, we will summarize the previous work in both directions, attacks and remedies with a focus on the authors' previous work in this domain. We will also discuss the research trends so that the emerging devices can better help secure our computing systems, besides their roles in extending the Moore's Law.","PeriodicalId":140647,"journal":{"name":"2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129111837","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Peipei Yin, Chenghua Wang, Weiqiang Liu, F. Lombardi
{"title":"Design and Performance Evaluation of Approximate Floating-Point Multipliers","authors":"Peipei Yin, Chenghua Wang, Weiqiang Liu, F. Lombardi","doi":"10.1109/ISVLSI.2016.15","DOIUrl":"https://doi.org/10.1109/ISVLSI.2016.15","url":null,"abstract":"Approximate/inexact computing has become an attractive approach for designing high performance and low power arithmetic circuits. Floating-point (FP) arithmetic is required in many applications, such as digital signal processing and machine learning. Different approximate FP multipliers are proposed in this paper, the accuracy and the circuit requirements of these designs are assessed to select the best approximate scheme as according to different metrics. It is shown that the proposed approximate single precision FP multiplier design reduces power consumption, area and delay by up to 61%, 55%, and 49% respectively compared with its exact counterpart while incurring in a moderate error, moreover this paper shows that the so-called IFPM24-15 multiplier is the most efficient design in terms of PDP and NMED compared with previous inexact FP multipliers. High dynamic range (HDR) images are processed using the proposed approximate FP multipliers to show the validity of the approximate design.","PeriodicalId":140647,"journal":{"name":"2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)","volume":" 2","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"113949163","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Fault-Tolerant FPGA with Column-Based Redundancy and Power Gating Using RRAM","authors":"Kibum Lee, S. Wong","doi":"10.1109/ISVLSI.2016.86","DOIUrl":"https://doi.org/10.1109/ISVLSI.2016.86","url":null,"abstract":"This paper presents a silicon-proven fault tolerant FPGA architecture that can repair a wide range of hardware faults. This new architecture does not require fine-grained location of fault, and the error map is stored in non-volatile memory that is monolithically integrated on top of the CMOS circuit. Redundancy operations are fully self-contained and do not affect data streaming in and out of the FPGA. The power gating scheme is implemented to save idle leakage power and fix hardware faults in the power network. The architecture has been verified in a test chip fabricated in 28nm technology. The maximum shift in performance after engaging redundancy is about 2% and the power footprint is unaffected.","PeriodicalId":140647,"journal":{"name":"2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133094484","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Honglan Jiang, Chengkun Shen, P. Jonker, F. Lombardi, Jie Han
{"title":"Adaptive Filter Design Using Stochastic Circuits","authors":"Honglan Jiang, Chengkun Shen, P. Jonker, F. Lombardi, Jie Han","doi":"10.1109/ISVLSI.2016.132","DOIUrl":"https://doi.org/10.1109/ISVLSI.2016.132","url":null,"abstract":"This paper proposes the design of an adaptive filter in stochastic circuits. The proposed circuit requires lower area and power than a conventional stochastic implementation. In the proposed design, the stochastic multiplier is implemented by an XNOR gate, as in a conventional scheme. However, the stochastic adder based on a multiplexer is not a very efficient implementation due to the three required stochastic number generators (SNGs) and the iterative operation required in the adaptive filter. Thus, a novel stochastic adder using a counter and a post processing unit is proposed. This adder avoids the use of SNGs, therefore it incurs a smaller area and power, while operating faster than the conventional (multiplexer-based) stochastic adder. In terms of accuracy and hardware efficiency, simulation results show that the adaptive filter using the proposed stochastic design outperforms the conventional stochastic implementation using linear feedback shift register (LFSR) based SNGs. Specifically, the proposed design consumes 35.81% less dynamic power and 21.34% less area than an LFSR-based implementation at a slightly higher accuracy.","PeriodicalId":140647,"journal":{"name":"2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)","volume":"117 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133319488","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Energy Optimization of Racetrack Memory-Based SIMON Block Cipher","authors":"S. Deb, A. Chattopadhyay, Hao Yu","doi":"10.1109/ISVLSI.2016.103","DOIUrl":"https://doi.org/10.1109/ISVLSI.2016.103","url":null,"abstract":"Spin-based memory devices are gaining importance due to multiple advantages like, zero standby power, high-write endurance and fast read, write operations. Besides storage, Spin Torque Transfer (STT)-based Magnetic Tunnel Junctions (MTJs) and Racetrack Memories (RMs) are also being investigated for logic applications, especially in the context of in-memory computing and neuromorphic architectures. Despite multiple innovations at technology-, device-and circuit-level, spin-based circuits suffer from poor energy efficiency, due to the high energy consumption of write operations. In this paper, we propose design optimizations to reduce the number of write operations in RM-based logic circuits, and therefore, achieve overall gain in energy performance. We performed in-depth study of the cutting-edge cryptographic primitive, block cipher SIMON, using experimentally validated Verilog-A models of MTJ and RM. For this benchmark, simulations demonstrate 4.65× reduction in computation energy, 2.66× improvement in computation delay and 1.71× reduction in transistor count compared to its base implementation using RM.","PeriodicalId":140647,"journal":{"name":"2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129237041","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
I. Agbo, M. Taouil, S. Hamdioui, P. Weckx, S. Cosemans, P. Raghavan, F. Catthoor, W. Dehaene
{"title":"Quantification of Sense Amplifier Offset Voltage Degradation due to Zero-and Run-Time Variability","authors":"I. Agbo, M. Taouil, S. Hamdioui, P. Weckx, S. Cosemans, P. Raghavan, F. Catthoor, W. Dehaene","doi":"10.1109/ISVLSI.2016.30","DOIUrl":"https://doi.org/10.1109/ISVLSI.2016.30","url":null,"abstract":"Nowadays, typical (memory) designers add design margins to compensate for uncertainties, however, this may be overestimated leading to yield loss, or underestimated leading to reduced reliability designs. Accurate quantification of all uncertainties is therefore critical to provide high quality and optimal designs. These uncertainties are caused by zero-time variability (due to process variability), and by run-time variability(due to environmental variabilities such as voltage and temperature, or due to temporal variability such as aging). This paper uses an accurate methodology to predict the impact of both zero-and run-time variability on the offset voltage of sense amplifiers while considering different workloads and PVT variations for a pre-defined failure rate. The results show a marginal impact of environmental run-time variability on the offset specification when considering zero-time variability only, while this becomes significant (up to 2X) when incorporating aging run-time variability. The results can be used to quantify whether the required offset voltage is met or not for the targeted lifetime, hence, enable the designer to take appropriate measures for an efficient and optimized design, depending on the targeted application lifetime.","PeriodicalId":140647,"journal":{"name":"2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122344789","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Scalable Integer DCT Architecture for HEVC Encoder","authors":"Maher Abdelrasoul, M. Sayed, V. Goulart","doi":"10.1109/ISVLSI.2016.98","DOIUrl":"https://doi.org/10.1109/ISVLSI.2016.98","url":null,"abstract":"HEVC (H.265) standard was proposed as a means to increase the compression rate with no loss in video quality. Large integer DCT, with sizes 16x16 and 32x32, is one of the key new features of the H.265 standard. In this paper, we propose a new scalable architecture for integer DCT in HEVC encoder. The proposed architecture is a fully pipelined architecture with optimized adders bit-widths. It was prototyped on TSMC 65 nm CMOS technology. The prototyping results show the high performance of theproposed architecture. Its gate count is 130K and it can achieve throughput of 9.26 Gsps. The proposed architecture can encode 8K @ 120 fps video sequence with working frequency of 373.25 MHz in real time.","PeriodicalId":140647,"journal":{"name":"2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114209383","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}