Fault-Tolerant FPGA with Column-Based Redundancy and Power Gating Using RRAM

This paper presents a silicon-proven fault tolerant FPGA architecture that can repair a wide range of hardware faults. This new architecture does not require fine-grained location of fault, and the error map is stored in non-volatile memory that is monolithically integrated on top of the CMOS circuit. Redundancy operations are fully self-contained and do not affect data streaming in and out of the FPGA. The power gating scheme is implemented to save idle leakage power and fix hardware faults in the power network. The architecture has been verified in a test chip fabricated in 28nm technology. The maximum shift in performance after engaging redundancy is about 2% and the power footprint is unaffected.