An Automated Hardware/Software Co-Design Flow for Partially Reconfigurable FPGAs

Partial reconfiguration (PR) enhances traditional FPGA-based reconfigurable embedded systems with benefits such as reduced resource requirements and increased functionality. Since fully realizing these PR benefits requires extensive PR design flow knowledge, as well as the target FPGA's low-level architectural details, PR has not yet gained widespread usage. To alleviate manual design-time effort, we present the design automation for partial reconfiguration (DAPR) design flow for hardware/software (HW/SW) co-designed systems. DAPR's design flow isolates low-level PR design complexities involved in analyzing PR designs with different performance parameters to make PR more amenable to designers.