Design of Low Power 5-Bit Hybrid Flash ADC

Abstract

In this paper, a low power 5-bit hybrid flash architecture is proposed. The proposed analog-to-digital converter (ADC) uses appropriate combination of both conventional double-tail comparators and standard cell comparators. Standard cell comparators are used to reduce power consumption. Thus, the proposed hybrid architecture results in extended dynamic range when compared to standard cell and thresholdinverter quantization (TIQ) based flash ADC. The proposedhybrid architecture is implemented in CMOS 180 nm N-welltechnology with 1.8 V supply. Simulation results show thepower reduction upto 48.47% when compared to conventionalarchitecture. The simulated spurious-free dynamic range (SFDR) is 38.54 dB and effective number of bits (ENOB) is 4.7 bits witha 1.22 MHz input at a sampling rate of 250 MS/s. The hybridADC consumes about 7.11 mW of power with figures of merit(FOM) of 1094.18 fJ/conversion-step.