A Low-Leakage, Robust ESD Clamp with Thyristor Delay Element in 65 nm CMOS Technology

Abstract

Electrostatic discharge (ESD) is a well-known problem in integrated circuits that affects its reliability, yield and cost. It is important to design ESD protection circuits that are ablet o prevent ESD related yield loss [1]. In this work, a 65 nm static clamp with a thyristor as a delay element to extend the on time of the clamp during the ESD event is presented. Simulation and measurement results show that the proposed clamp has fast response for ESD-like events. Extensive analysis demonstrates that the clamp is stable against false triggering, power supplynoise and has very low-leakage current. Measurement resultsshow that the clamp is capable of handling 3.21A of currentwhile its leakage is only 180pA. In addition, the measurementresults show that the proposed clamp demonstrates immunityagainst false triggering under the fast power-on condition.