Design and Characterization of the TERO-PUF on SRAM FPGAs

Physical unclonable functions (PUF) are a promising approach in design for trust and security. A PUF derives a unique identifier for different similar dies using some of their physical characteristics, so it can be used to authenticate chips and to fight against counterfeiting and theft of devices. The transient effect ring oscillator (TERO) PUF is based on the extraction of the entropy of the process variations by comparison between TERO cells characteristics. This TERO cell needs to be carefully designed in order to construct a PUF. This task needs to be done with precision, especially in the size of used gates and in the delays of all connections inside the cell. This is particularly challenging in FPGA. This paper presents the design of TERO cells in two FPGA families: Xilinx Spartan 6 and Altera Cyclone V. Additionally, results of the characterization of the TEROPUF are presented and compared for the two technologies. The reproducibility of experimental results are guaranteed by the online access to all design files.