Synthesizing Asynchronous Circuits toward Practical Use

Abstract

This work proposes a new method of synthesizing asynchronous circuits targeting its practical usability. The key contribution of this work is finding an effective technique of inter-mixing the two design principles namely handshaking based single-rail and timing annotated (i.e., delay insensitive) dual-rail of asynchronous circuits. Precisely, we propose clever ways of partitioning an input (synchronous) circuit to transform it into a circuit with single-rail and dual-rail sub-circuits and of designing seamless interface to stitch the sub-circuits to achieve partial or full combinations of high-performance, low-power consumption, great immunity to delay and noise variability in low-voltage designs, and mitigating side-channel attacks in hardware security.