A 90-nm CMOS Frequency Synthesizer with a Tripler for 60-GHz Wireless Communication Systems

Abstract

The paper presents the design and realization of a frequency synthesizer for 60-GHz wireless communication systems. Implemented with 90nm CMOS technology, the phase-locked loop based frequency synthesizer includes a high-frequency voltage-controlled oscillator (VCO), a high-speed divider, a programmable divider, a charge pump, and a frequency tripler. The programmable divider is used to offer channel-switched function for frequency synthesis. To lower the power consumption of the frequency synthesizer, the 15 GHz wideband VCO is employed and generates the fundamental and second harmonic signals for frequency mixing a triple signal. The measured phase noise for VCO at 17.76-GHz frequency is -97.05 dBc/Hz at 1MHz offset. The proposed frequency synthesizer provides the tuning range from 44 to 53 GHz and dissipates 55 mW in the whole circuit.