{"title":"具有电荷模式自适应的集成共门CTLE接收机前端","authors":"Divya Duvvuri, V. Pasupureddi","doi":"10.1109/ISVLSI.2016.105","DOIUrl":null,"url":null,"abstract":"This work presents a first common gate continuous time linear equalizer (CG-CTLE) with charge mode adaptation in 1.1 V, 65 nm CMOS technology. The proposed equalizer is realized with a common gate topology and offers an input impedance of 50 Ω. It also acts as a first stage of current mode receiver and is made adaptive to varying channel loss. Therefore, the need for an external termination to avoid reflections and the need for a trans-impedance amplifier as receiver's first stage is eliminated. The proposed CG-CTLE is compared with conventional common source (CS) CTLE and it outperforms CSCTLE in terms of bandwidth and bit error rate (BER) for the same targeted output signal swing and power consumption. The post layout performance results show that it offers an input impedance of 44.6 Ω, input referred noise of 19.6 √pA/Hz, BER = 10-13 and consumes 13.9 mW power while operating at a data rate of 15 Gbps over a 7.5 inch FR4 PCB trace.","PeriodicalId":140647,"journal":{"name":"2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2016-07-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"An Integrated Common Gate CTLE Receiver Front End with Charge Mode Adaptation\",\"authors\":\"Divya Duvvuri, V. Pasupureddi\",\"doi\":\"10.1109/ISVLSI.2016.105\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This work presents a first common gate continuous time linear equalizer (CG-CTLE) with charge mode adaptation in 1.1 V, 65 nm CMOS technology. The proposed equalizer is realized with a common gate topology and offers an input impedance of 50 Ω. It also acts as a first stage of current mode receiver and is made adaptive to varying channel loss. Therefore, the need for an external termination to avoid reflections and the need for a trans-impedance amplifier as receiver's first stage is eliminated. The proposed CG-CTLE is compared with conventional common source (CS) CTLE and it outperforms CSCTLE in terms of bandwidth and bit error rate (BER) for the same targeted output signal swing and power consumption. The post layout performance results show that it offers an input impedance of 44.6 Ω, input referred noise of 19.6 √pA/Hz, BER = 10-13 and consumes 13.9 mW power while operating at a data rate of 15 Gbps over a 7.5 inch FR4 PCB trace.\",\"PeriodicalId\":140647,\"journal\":{\"name\":\"2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)\",\"volume\":\"19 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2016-07-11\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISVLSI.2016.105\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISVLSI.2016.105","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
An Integrated Common Gate CTLE Receiver Front End with Charge Mode Adaptation
This work presents a first common gate continuous time linear equalizer (CG-CTLE) with charge mode adaptation in 1.1 V, 65 nm CMOS technology. The proposed equalizer is realized with a common gate topology and offers an input impedance of 50 Ω. It also acts as a first stage of current mode receiver and is made adaptive to varying channel loss. Therefore, the need for an external termination to avoid reflections and the need for a trans-impedance amplifier as receiver's first stage is eliminated. The proposed CG-CTLE is compared with conventional common source (CS) CTLE and it outperforms CSCTLE in terms of bandwidth and bit error rate (BER) for the same targeted output signal swing and power consumption. The post layout performance results show that it offers an input impedance of 44.6 Ω, input referred noise of 19.6 √pA/Hz, BER = 10-13 and consumes 13.9 mW power while operating at a data rate of 15 Gbps over a 7.5 inch FR4 PCB trace.