Reliable Many-Core System-on-Chip Design Using K-Node Fault Tolerant Graphs

Abstract

State-of-the-art techniques for enhancing system-level reliability for SoCs include both design-time and run-time strategies, such as task mapping and reliable communication network design. In contrast to task mapping where the network topology is predefined, fault-tolerance in the communication network design involves the reliability evaluation of the network topology. In this paper, we apply the idea of k-node fault tolerant graph to address the challenge of reliable network design. To determine k-node fault tolerant graph for an arbitrary subject graph is non-trivial. We propose a heuristic based on divide-and-conquer approach and validate the quality of the results with an exhaustive search for small graphs. The effectiveness of proposed methodology is demonstrated with real multiprocessor computational task using a commercial system-level design environment.