2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)最新文献

{"title":"Area Efficient Hardware Architecture for Implicitly-Defined Complex Events Processing","authors":"M. Tahghighi, Wei Zhang, Sharad Sinha","doi":"10.1109/ISVLSI.2016.130","DOIUrl":"https://doi.org/10.1109/ISVLSI.2016.130","url":null,"abstract":"Complex Event Processing refers to different mechanisms such as event correlation and event patterns detection for processing multiple events with the goal of inferring the complicated ones. While a simple event may provide trivial information, combining several of them can help in deriving more useful information. Detecting the complex events requires huge processing capability. The existing hardware designs for complex events detection all target explicitly defined events. However, there are many scenarios that some of the events may not be explicitly known ahead of detection. To address this challenge, in this work we propose a general complex event detection methodology which is capable to deal with implicitly-defined events. The concepts of dynamic state machine, and context switching mechanism are introduced and an area-efficient iterative architecture is developed on FPGA to detect the implicitly-defined complex events. The experiment results demonstrate the effectiveness of proposed architecture.","PeriodicalId":140647,"journal":{"name":"2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)","volume":"90 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115847694","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Multiple-Bit-Flip Detection Scheme for a Soft-Error Resilient TCAM","authors":"Infall Syafalni, Tsutomu Sasao, X. Wen","doi":"10.1109/ISVLSI.2016.77","DOIUrl":"https://doi.org/10.1109/ISVLSI.2016.77","url":null,"abstract":"Ternary content addressable memories (TCAMs) are special memories which are widely used in high-speed network applications such as routers, firewalls, and network address translators. In high-reliability network applications such as aerospace and defense systems, soft-error tolerant TCAMs are indispensable to prevent data corruption or faults caused by radiation. This paper proposes a novel soft-error tolerant TCAM for multiple-bit-flip errors using partial don't-care keys (X-keys), called k-TX. k-TX corrects up to k-bit flip errors and significantly enhances the tolerance of the TCAM against soft errors, where k is the maximum number of bit flips in a word of a TCAM. k-TX consists of a TCAM, a preprocessed don't-care-bit index look-up memory (X look-up), and an ECC-SRAM. First, k-TX randomly selects a search key. After that, k-TX detects multiple-bit-flip errors by the generated X-keys using the X look-up. If the keys match the different locations, then a soft error is suspected and k-TX refreshes the TCAM words by using a backup ECC-SRAM. Experimental results show that the soft-error tolerance capability of k-TX outperforms other schemes significantly. Moreover, the hardware overhead of k-TX is small due to the use of only a single TCAM. k-TX can be easily implemented and is useful for fault-tolerant packet classifiers.","PeriodicalId":140647,"journal":{"name":"2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)","volume":"236 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123736096","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"On Time Redundancy of Fault Tolerant C-Based MPSoCs","authors":"Anjana Balachandran, Nandeesha Veeranna, Benjamin Carrión Schäfer","doi":"10.1109/ISVLSI.2016.99","DOIUrl":"https://doi.org/10.1109/ISVLSI.2016.99","url":null,"abstract":"Most prior work on hardware reliability make use of module (spatial) redundancy or time redundancy. In the first case, these methods assume that each module is exactly the same. Multiple module replicas implementing the same logic function are executed in different hardware channels and a voting scheme detects if the outputs match or not. In the second case, they re-compute the result using the same hardware channel. These previous works mainly applies at the RT-level. In this work we investigate the use of time redundancy to increase the reliability of C-Based MPSoCs. The method presented in this work leverages the latest system-level design capabilities of commercial HLS tools that allow the design, simulation and verification of complete SoCs at the behavioral level. Our proposed method builds complete MPSoCs at the behavioral level, which contain a variety of loosely coupled Hardware Accelerators (HWAccs) mapped as slaves onto a memory mapped shared bus. Inactive time at each HWAcc, mainly due to read and write overheads between the masters and slaves and bus congestion problems, is then used to recompute the output twice or thrice. This allows to detect if a transient fault has occurred or even fully mask the fault for the case that the results is re-computed three times. Although the proposed method cannot guarantee complete fault tolerance, experimental results show that especially for larger MPSoCs it can in most of the cases at least recompute the output twice and thus detect if a fault has occurred.","PeriodicalId":140647,"journal":{"name":"2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131892599","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Accelerating Particle Filter on FPGA","authors":"B. G. Sileshi, J. Oliver, C. Ferrer","doi":"10.1109/ISVLSI.2016.66","DOIUrl":"https://doi.org/10.1109/ISVLSI.2016.66","url":null,"abstract":"Particle filters (PFs) are Bayesian based estimation algorithms with attractive theoretical properties for addressingwide range of complex applications that are nonlinear and nonGaussian. However, they are associated with a huge computational demand which limited their application in most realtime systems. To address such a drawback in PFs, this paper presents different approaches for PFs acceleration based on afield programmable gate arrays (FPGAs).","PeriodicalId":140647,"journal":{"name":"2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132127394","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Leveraging Compiler Support on VLIW Processors for Efficient Power Gating","authors":"J. S. P. Giraldo, L. Carro, Stephan Wong, A. C. S. Beck","doi":"10.1109/ISVLSI.2016.70","DOIUrl":"https://doi.org/10.1109/ISVLSI.2016.70","url":null,"abstract":"Energy consumption has long been one of the main constraints that has guided the design of embedded processors. VLIW architectures are well-suited for this field, since they have a simpler microarchitecture and reduced energy consumption due to their static ILP exploitation. As we will show in this paper, intelligent use of the compiler allows for power gating at a finer grain (i.e., functional units, registers), saving considerable amounts of power -- which is not possible in superscalar processors. We do so by inserting customized instructions at compile time, based on the analysis that involves probabilities of conditional branches and basic block information obtained via dynamic profiling. By using our compiler technique, it is possible to save up of 20% in the total energy consumption with marginal losses in performance.","PeriodicalId":140647,"journal":{"name":"2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132207471","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"On Area-Efficient Implementation of Data Delays in 7 Series Xilinx FPGAs","authors":"M. Parfieniuk, S. Park","doi":"10.1109/ISVLSI.2016.14","DOIUrl":"https://doi.org/10.1109/ISVLSI.2016.14","url":null,"abstract":"For 7 series Xilinx FPGAs, this paper shows that it is risky to believe that so fundamental operation as data delay must be always implemented without wasting chip area, even when design tools are not especially guided by a developer. Against this background, two solutions are presented that allow for minimizing the area occupied by flip-flops used to delay data that comes from outside the slices containing these flipflops. Both approaches are based on exploiting the additional storage elements that are present in slices of 7 series FPGAs. The implicit solution is to constrain floorplanning, while the explicit solution requires quite advanced and tricky HDL coding: low-level primitives must be instantiated, including LUTs in the 2-output mode. For both approaches, we describe in detail how to enable the additional register in order to save slices. Our research was aimed at designing FIR filters for digital signal processing.","PeriodicalId":140647,"journal":{"name":"2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)","volume":"135 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133762060","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Improving the Functional Test Delay Fault Coverage: A Microprocessor Case Study","authors":"Aymen Touati, A. Bosio, P. Girard, A. Virazel, P. Bernardi, M. Reorda","doi":"10.1109/ISVLSI.2016.42","DOIUrl":"https://doi.org/10.1109/ISVLSI.2016.42","url":null,"abstract":"Functional test guarantees that the circuit is tested under normal conditions, thus avoiding any over-as well as under-test issues. This work is based on the use of Software-Based-Self-Test that allows a special application of functional test to the processor-based systems. This strategy applies the so-called functional test programs that are executed by the processor to guarantee a given fault coverage. The main goal of this paper is to investigate a methodology to improve the delay fault coverage of a given test set of functional test programs. We propose to exploit existing Design-for-Test architecture to apply in a smarter way the functional programs. Then, we combine those programs with the classical at-speed LOC and LOS delay fault testing schemes to further increase the delay fault coverage. Results show that it is possible to achieve a global test solution able to maximize the delay fault coverage.","PeriodicalId":140647,"journal":{"name":"2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)","volume":"193 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132949920","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Computing in Ribosomes: Performing Boolean Logic Using mRNA-Ribosome System","authors":"P. Chatterjee, Mayukh Sarkar, P. Ghosal","doi":"10.1109/ISVLSI.2016.128","DOIUrl":"https://doi.org/10.1109/ISVLSI.2016.128","url":null,"abstract":"Continuous increase in bottlenecks with silicon-based conventional computers inspired researchers around the world to search for a non-conventional computing alternative that led to the development of DNA Computing, Quantum Computing etc. Each computing technologies came with their own advantages and disadvantages. Biology has inspired the computing through the pathway of DNA Computing. Since its inception it has been proven to be a powerful approach to solve computationally hard problems. But to solve otherwise general problems it needs mathematical ability. It lacks this ability in the sense that several manual interventions are required here. Moreover, the biomolecular operations in the DNA Labs are also slow to perform. To overcome this another molecule residing in the cell viz. ribosome can be used. Its automated procedure of translation can be used to perform the required operation. Recent development of artificial ribosome and the possibility of mutations in rRNAs residing in the ribosome has enabled the pathway of computation without any manual interventions. It can operate automatically at the speed of natural operations getting performed inside a living cell. This work has proposed a pathway to perform logic operations using the ribosomes.","PeriodicalId":140647,"journal":{"name":"2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128960710","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Seamlessly Pipelined Shift-and-Add Circuits Based on Precise Delay Analysis and Its Applications","authors":"Tso-Bing Juang, Ying-Ren Lee","doi":"10.1109/ISVLSI.2016.49","DOIUrl":"https://doi.org/10.1109/ISVLSI.2016.49","url":null,"abstract":"Shift-add/subtract circuits constitute the basic building blocks of several frequently used complex arithmetic units such as multiple constant multipliers, exponentiation circuits, fast division circuits, CORDIC rotators, logarithmic and residue number conversation units, etc. Fine-grained pipelined designs of these arithmetic units have strong potential to improve the power-performance-reliability profile of several compute-intensive and constraint-driven applications like digital signal processing, cryptography, and communication. Efficient pipelining of these circuits therefore requires precise analysis of propagation delay of its basic blocks like shift-add/subtract circuits and connected shift-add arrays. Moreover, careful pipelining of shift-add/subtract circuits has strong potential to enhance the throughput of complex arithmetic units where they are embodied. In this paper, we derive seamlessly pipelined shift-add/subtract circuits to achieve a desired critical path delay based on the throughput requirement of the embodying arithmetic units and application environment. We aim at providing a brief demonstration of how the pipelined shift-add/subtract circuits could used to enhance the performance and reduce power consumption of some typical constraint-driven computations. It has been observed that shift-add based logarithmic/antilogarithmic converters achieve area-efficient and high-performance inter-conversion between binary numbers and logarithmic numbers with low approximation errors to be used efficiently for logarithmic number system (LNS)-based computations. In this paper, we show that the use of seamlessly pipelined shift-adds/subtract circuits provide remarkable improvement of logarithmic/antilogarithmic converters over the conventional ones, and can be used in the LNS-based computing system to boost the performance and reduce the overall energy consumption. We have also shown how throughput rate of high-precision exponentiation circuits can be enhanced by seamlessly pipelined shift-add circuits for cryptographic applications.","PeriodicalId":140647,"journal":{"name":"2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114274006","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Phase-Based Dynamic Instruction Window Optimization for Embedded Systems","authors":"Tosiron Adegbija, A. Gordon-Ross","doi":"10.1109/ISVLSI.2016.96","DOIUrl":"https://doi.org/10.1109/ISVLSI.2016.96","url":null,"abstract":"Even though much previous work explores adapting instruction queue (IQ) and reorder buffer (ROB) sizes to application requirements, traditional IQ/ROB optimizations may be prohibitive for resource-constrained embedded systems, due to the hardware/execution time overheads. We propose low overhead, phase-based instruction window optimization to dynamically vary IQ and ROB sizes for different execution phases based on the applications' variable execution characteristics. Results show that our methodology reduces both the average execution time and energy consumption by 23%, compared to a base system with fixed IQ/ROB sizes.","PeriodicalId":140647,"journal":{"name":"2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)","volume":"149 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123057494","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}