FPGA加速粒子滤波

2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2016-07-01 DOI:10.1109/ISVLSI.2016.66

B. G. Sileshi, J. Oliver, C. Ferrer

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引用次数: 12

摘要

粒子滤波(PFs)是一种基于贝叶斯的估计算法，具有很好的理论特性，可用于处理各种非线性和非高斯的复杂应用。然而，它们与巨大的计算需求相关联，这限制了它们在大多数实时系统中的应用。为了解决PFs的这一缺陷，本文提出了基于现场可编程门阵列(fpga)的PFs加速的不同方法。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Accelerating Particle Filter on FPGA

Particle filters (PFs) are Bayesian based estimation algorithms with attractive theoretical properties for addressingwide range of complex applications that are nonlinear and nonGaussian. However, they are associated with a huge computational demand which limited their application in most realtime systems. To address such a drawback in PFs, this paper presents different approaches for PFs acceleration based on afield programmable gate arrays (FPGAs).

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来源期刊

2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)

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