On Time Redundancy of Fault Tolerant C-Based MPSoCs

Abstract

Most prior work on hardware reliability make use of module (spatial) redundancy or time redundancy. In the first case, these methods assume that each module is exactly the same. Multiple module replicas implementing the same logic function are executed in different hardware channels and a voting scheme detects if the outputs match or not. In the second case, they re-compute the result using the same hardware channel. These previous works mainly applies at the RT-level. In this work we investigate the use of time redundancy to increase the reliability of C-Based MPSoCs. The method presented in this work leverages the latest system-level design capabilities of commercial HLS tools that allow the design, simulation and verification of complete SoCs at the behavioral level. Our proposed method builds complete MPSoCs at the behavioral level, which contain a variety of loosely coupled Hardware Accelerators (HWAccs) mapped as slaves onto a memory mapped shared bus. Inactive time at each HWAcc, mainly due to read and write overheads between the masters and slaves and bus congestion problems, is then used to recompute the output twice or thrice. This allows to detect if a transient fault has occurred or even fully mask the fault for the case that the results is re-computed three times. Although the proposed method cannot guarantee complete fault tolerance, experimental results show that especially for larger MPSoCs it can in most of the cases at least recompute the output twice and thus detect if a fault has occurred.