Area Efficient Hardware Architecture for Implicitly-Defined Complex Events Processing

Abstract

Complex Event Processing refers to different mechanisms such as event correlation and event patterns detection for processing multiple events with the goal of inferring the complicated ones. While a simple event may provide trivial information, combining several of them can help in deriving more useful information. Detecting the complex events requires huge processing capability. The existing hardware designs for complex events detection all target explicitly defined events. However, there are many scenarios that some of the events may not be explicitly known ahead of detection. To address this challenge, in this work we propose a general complex event detection methodology which is capable to deal with implicitly-defined events. The concepts of dynamic state machine, and context switching mechanism are introduced and an area-efficient iterative architecture is developed on FPGA to detect the implicitly-defined complex events. The experiment results demonstrate the effectiveness of proposed architecture.