Leveraging Compiler Support on VLIW Processors for Efficient Power Gating

Abstract

Energy consumption has long been one of the main constraints that has guided the design of embedded processors. VLIW architectures are well-suited for this field, since they have a simpler microarchitecture and reduced energy consumption due to their static ILP exploitation. As we will show in this paper, intelligent use of the compiler allows for power gating at a finer grain (i.e., functional units, registers), saving considerable amounts of power -- which is not possible in superscalar processors. We do so by inserting customized instructions at compile time, based on the analysis that involves probabilities of conditional branches and basic block information obtained via dynamic profiling. By using our compiler technique, it is possible to save up of 20% in the total energy consumption with marginal losses in performance.